SL74LV373 데이터 시트보기 (PDF) - System Logic Semiconductor

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SL74LV373

OCTAL D-TYPE TRANSPARENT LATCH (3-State)

System Logic Semiconductor 

SL74LV373

AC CHARACTERISTICS (CL=50 pF, tLH = tHL = 6.0 ns)

Symbol

Parameter

Test

conditions

tPHL, tPLH Propagation delay Figure 1

from Dn to Qn

tPHL, tPLH Propagation delay Figure 2

from LE to Qn

tPHZ tPLZ

3-state output

from OE to Qn enable time

Figure 4

tPZH tPZL 3-state disable

from OE to Qn time

Figure 4

tTHL, tTLH

tW

HIGH-to-LOW and Figures 1,2

LOW-to-HIGH

transition time

Clock pulse width Figure 2

HIGH or LOW

tSU

Set-up time Dn to Figure 3

LE

tH

Hold time Dn to Figure 3

LE

CI

Input capacitance

CPD

Power dissipation VI = 0 V or

capacitance (per VCC

flip-flop)

VCC,

Limits

V

25°C -40°C to 85°C

125°C

min max min max min max

1.2 - 150 - 190 -

220

2.0 - 38 - 48 -

58

3.0 - 23 - 29 -

35

1.2 - 180 - 230 -

270

2.0 - 45 - 56 -

68

3.0 - 27 - 34 -

41

1.2 - 160 - 200 -

240

2.0 - 35 - 43 -

45

3.0 - 23 - 28 -

32

1.2 - 160 - 200 -

240

2.0 - 40 - 50 -

60

3.0 - 24 - 30 -

36

1.2 - 75 - 100 -

120

2.0 - 16 - 20 -

24

3.0 - 10 - 13 -

15

1.2 250 - 350 - 450 -

2.0 30 - 34 - 41

-

3.0 18 - 20 - 24

-

1.2 45 - 50 - 100 -

2.0 15 - 17 - 15

-

3.0 9 - 10 - 12

-

1.2 25 - 25 - 25

-

2.0 5 - 5

-

5

-

3.0 5 - 5

-

5

-

3.0 - 7 -

-

-

-

3.0 - 80 -

-

-

-

Unit

ns

pF

SLS System Logic

Semiconductor

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