SL74LV373 데이터 시트보기 (PDF) - System Logic Semiconductor
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SL74LV373 Datasheet PDF : 8 Pages
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SL74LV373
OCTAL D-TYPE TRANSPARENT LATCH
(3-State)
SL74LV373 are compatible by pinning with SL74HC373 and
SL74HCT373 series. Input voltage levels are compatible with
standard CMOS levels.
• Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL ICS
• Voltage supply range: 2.0 to 3.2 V
• LOW input current: 1.0 µÀ; 0.1 µÀ at Ò = 25 °Ñ
• Input current LOW/HIGH: 8 mÀ
• Latch current: not less than 150 mÀ at Ò = 125 °Ñ
• ESD acceptable value: not less than 2000 V as per HBM and
not less than 200 V as per MM
•
BLOCK DIAGRAM
ORDERING INFORMATION
SL74LV373N Plastic DIP
SL74LV373D SOIC
TA = -40° to 125° C
for all packages
03
D0
04
D1
07
D2
08
D3
13
D4
14
D5
17
D6
18
D7
11
LE
01
OE
Pin 20=VCC
Pin 10 = GND
02
Q0
05
Q1
06
Q2
09
Q3
12
Q4
15
Q5
16
Q6
19
Q7
PIN ASSIGNMENT
OE 01
Q0 02
D0 03
D1 04
Q1 05
Q2 06
D2 07
D3 08
Q3 09
GND 10
373
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 LE
FUNCTION TABLE
Inputs
Output
OE
LE
L
H
L
H
L
L
H
X
Dn
Qn
H
H
L
L
X
no change
X
Z
SLS System Logic
Semiconductor
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