HCC4001BDG 데이터 시트보기 (PDF) - STMicroelectronics

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HCC4001BDG

Rad-hard, high voltage, CMOS logic series

STMicroelectronics 

HCC40xxx, HCC45xxx

4

Radiations

Radiations

4.1

Total ionizing dose (TID)

All devices of the HCC series are 100 krad guaranteed as per the test methods described in Table 4.

Table 4. TID test conditions for the CMOS4000B family

Test parameter

Test conditions

Total dose

Dose rate

Sampling

Bias

conditions(1)

Limits

100 krad(Si)

40 krad(Si)/h

4 biased parts by wafer on 3 wafer per diffusion lot plus 1 control part to qualify the

wafer lot. In case one wafer fails, qualification is done wafer per wafer on 4 biased

parts

VDD = 10 V(2)

inputs at Vdd(3)

|∆ VTHN| < 2 V, |∆ VTHP| < 2 V

VTHN, VTHP, IOL, IOH, TPHL, TPLH, VOL, VOH, VN, VP, VH: see section 2.3.1 of the

“ESCC detail specification”, limits ± 35 % for high and low limits

Others tests performed as defined in section 2.3.1 of the “ESCC detail

specification” with corresponding limits

1. During irradiation

2. Vdd = 10 Volt has been demonstrated to be the worst case condition during characterization

3. Whenever functionally pertinent

Figure 2. Irradiation test flow

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1. The post rad guaranteed Vcc min is therefore 5 V.

DocID17102 Rev 7

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