M48T02 데이터 시트보기 (PDF) - STMicroelectronics

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M48T02

CMOS 2K x 8 TIMEKEEPER SRAM

STMicroelectronics 

Figure 3. Block Diagram

M48T02, M48T12

32,768 Hz

CRYSTAL

LITHIUM

CELL

OSCILLATOR AND

CLOCK CHAIN

8 x 8 BiPORT

SRAM ARRAY

POWER

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

VPFD

BOK

2040 x 8

SRAM ARRAY

A0-A10

DQ0-DQ7

E

W

G

VCC

VSS

AI01329

clock information in the bytes with addresses 7F8h-

7FFh. The clock locations contain the year, month,

date, day, hour, minute, and second in 24 hour BCD

format. Corrections for 28, 29 (leap year), 30, and

31 day months are made automatically. Byte 7F8h

is the clock control register. This byte controls user

access to the clock information and also stores the

clock calibration setting.

The eight clock bytes are not the actual clock

counters themselves; they are memory locations

consisting of BiPORT™ read/write memory cells.

The M48T02,12 includes a clock control circuit

which updates the clock bytes with current informa-

tion once per second. The information can be

accessed by the user in the same manner as any

other location in the static memory array.

The M48T02,12 also has its own Power-fail Detect

circuit. The control circuitry constantly monitors the

single 5V supply for an out of tolerance condition.

When VCC is out of tolerance, the circuit write

protects the SRAM, providing a high degree of data

security in the midst of unpredictable system opera-

tion brought on by low VCC. As VCC falls below

approximately 3V, the control circuitry connects the

battery which maintains data and clock operation

until valid power returns.

AC MEASUREMENT CONDITIONS

Input Rise and Fall Times

Input Pulse Voltages

Input and Output Timing Ref. Voltages

≤ 5ns

0.6V to 2.4V

0.8V to 2.2V

Note that Output Hi-Z is defined as the point where data

is no longer driven.

Figure 4. AC Testing Load Circuit

5V

DEVICE

UNDER

TEST

1kΩ

1.8kΩ

OUT

CL = 100pF

CL includes JIG capacitance

AI01019

3/14

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