M48T02 데이터 시트보기 (PDF) - STMicroelectronics
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M48T02 Datasheet PDF : 14 Pages
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Figure 10. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
M48T02, M48T12
AI00594
Two methods are available for ascertaining how
much calibration a given M48T02,12 may require.
The first involves simply setting the clock, letting it
run for a month and comparing it to a known accu-
rate reference (like WWV broadcasts). While that
may seem crude, it allows the designer to give the
end user the ability to calibrate his clock as his
environment may require, even after the final prod-
uct is packaged in a non-user serviceable enclo-
sure. All the designer has to do is provide a simple
utility that accesses the Calibration byte. The utility
could even be menu driven and made foolproof.
The second approach is better suited to a manu-
facturing environment, and involves the use of
some test equipment. When the Frequency Test
(FT) bit, the seventh-most significant bit in the Day
Register, is set to a ’1’, and the oscillator is running
at 32,768 Hz, the LSB (DQ0) of the Seconds Reg-
ister will toggle at 512 Hz. Any deviation from 512
Hz indicates the degree and direction of oscillator
frequency shift at the test temperature. For exam-
ple, a reading of 512.01024 Hz would indicate a
+20 PPM oscillator frequency error, requiring a
-10(001010) to be loaded into the Calibration Byte
for correction. Note that setting or changing the
Calibration Byte does not affect the Frequency test
output frequency. The device must be selected and
addresses must stable at Address 7F9h when read-
ing the 512 Hz on DQ0.
The FT bit must be set using the same method used
to set the clock, using the Write bit. The LSB of the
Seconds Register is monitored by holding the
M48T02,12 in an extended read of the Seconds
Register, without having the Read bit set. The FT
bit MUST be reset to ’0’ for normal clock operations
to resume.
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