LH28F160BJHE-TTL90 데이터 시트보기 (PDF) - Sharp Electronics

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LH28F160BJHE-TTL90

Flash Memory 16M (1M × 16/2M × 8)

Sharp Electronics 

LHFI 6JO4

15

4.10 Set Block and Permanent Lock-Bit

Commands

A flexible block locking and unlocking scheme is enabled

via a combination of block lock-bits. a permanent lock-bit

and WP# pin. The block lock-bits and WP# pin gates

program and erase operations while the permanent lock-bit

gates block-lock bit modification. With the permanent

lock-bit not set, individual block lock-bits can be set using

the Set Block Lock-Bit command. The Set Permanent

Lock-Bit command. sets the permanent lock-bit. After the

permanent lock-bit is set, block lock-bits and locked block

contents cannot altered. See Table 5 for a summary of

hardware and software write protection options.

Set block lock-bit and-permanent lock-bit are executed by

1 two-cycle command sequence. The set block or

aermanent lock-bit setup along with appropriate block or

device address is written followed by either the set block

ock-bit confirm (and an address within the block to be

ocked) or the set permanent lock-bit confirm (and any

ievice address). The WSIM then controls the set lock-bit

Algorithm. After the sequence is written, the device

automatically outputs status resister data when read (see

:&tire IO). The CPU can detect the completion of the set

ock-bit event by analyzing the RY/BY# pin output or

tatus register bit SR.7.

Nhen the set lock-bit operation is complete, status register

bit SR.4 should be checked. If an error is detected, the

tatus register should be cleared. The CUI will remain in

ead status register mode until a new command is issued.

his two-step sequence of set-up followed by execution

nsures that lock-bits are not accidentally set. An invalid

‘et Block or Permanent Lock-Bit command will result in

tatus register bits SR.4 and SR.5 being set to “1”. Also,

:liable operations occur only when Vcc=2.7V-3.6V and

rCCW=vCCWHIR~ In the absence of this high voltage,

)ck-bit contents are protected against alteration.

i successful set block lock-bit operation requires that the

ermanent lock-bit be cleared. If it is attempted with the

ermanent lock-bit set. SR.1 and SR.4 will be set to “1”

?d the operation will fail.

4.1 I Clear Block Lock-Bits Command

All set block lock-bits are cleared in parallel via the Clea

Block Lock-Bits command. With the permanent lock-bi

not set. block lock-bits can be cleared using only the Clea

Block Lock-Bits command. If the permanent lock-bit i:

set, block lock-bits cannot cleared. See Table 5 for ;

summary of hardware and software write protectior

options.

Clear block lock-bits operation is executed by a two-cycle

command sequence. A clear block lock-bits setup is firs

written. After the command is written. the device

automatically outputs status register data when read (set

Figure 11). The CPU can detect completion of the cleai

block lock-bits event by analyzing the RY/BY# Pin outpu’

or status register bit SR.7.

When the operation is complete. status register bit SR.5

should be checked. If a clear block lock-bit error is

detected. the status register should be cleared. The GUI

will remain in read status register mode until another

command is issued.

This two-step sequence of set-up followed by execution

ensures that block lock-bits are not accidentally cleared.

An invalid ClearBlock Lock-Bits commandsequencewill

result in statusregisterbitsSR.4andSR.5beingsetto “1”.

Also, a reliable clear block lock-bits operationcan only

occur when V,,=2.7V-3.6V and VCCW=VCCWHt,,.If a

clear block lock-bits operation is attempted-while

VCCWIVCCwtK, SR.3and SR.5will be setto “1”. In the

absenceof this high voltage, the block lock-bits content

are protected againstalteration.A successfucl lear block

lock-bits operationrequiresthat the permanentlock-bit is

not set. If it is attemptedwith the permanentlock-bit set.

SR.1 and SR.5 will be setto “1” and the operationwill

fail.

If a clearblock lock-bitsoperationis aborteddueto Vccw

or V,, transitioninp out of valid range or RP# active

transition, block lock-bit values are left in an

undeterminedstate. A repeatof clear block lock-bits is

required to initialize block lock-bit contents to known

values. Once the permanentlock-bit is set. it cannot be

cleared.

Rev. 1.25

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