MC100LVEL56 데이터 시트보기 (PDF) - ON Semiconductor
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MC100LVEL56 Datasheet PDF : 6 Pages
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MC100LVEL56
VCC Q0
20 19
Q0 SEL0
SEL1 VCC Q1 Q1 VEE
18 17 16 15 14 13 12 11
1
0
1
0
1
2
3
4
5
6
7
8
9 10
D0a D0a VBBO D0b D0b D1a D1a VBB1 D1b D1b
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. 20-Lead Package (Top View) and Logic Diagram
Table 1. PIN DESCRIPTION
PIN
D0a* − D1a*
D0a* − D1a*
D0b* − D1b*
D0b* − D1b*
FUNCTION
ECL Input Data a
ECL Input Data a Invert
ECL Input Data b
ECL Input Data b Invert
SEL0* − SEL1*
COM_SEL*
ECL Indiv. Select Input
ECL Common Select Input
VBB0, VBB1
Q0 − Q1
Q0 − Q1
Output Reference Voltage
ECL True Outputs
ECL Inverted Outputs
VCC
Positive Supply
VEE
Negative Supply
* Pins will default LOW when left open.
Table 2. TRUTH TABLE
Q0,
Q1,
SEL0 SEL1 COM_SEL Q0
Q1
X
X
L
L
L
H
H
H
H
L
H
a
a
L
b
b
L
b
a
L
a
a
L
a
b
Table 3. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Device Model
Moisture Sensitivity, (Note 1)
Pb-Free
Flammability Rating
Oxygen Index
Transistor Count
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Value
75 KW
N/A
> 2 kV
> 200 V
> 4 kV
Level 3
UL 94 V−0 @ 0.125 in
28 to 34
147
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