PTM1300 데이터 시트보기 (PDF) - Philips Electronics

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PTM1300

Programmable Media Processor

Philips Electronics 

MEMORY SYSTEM OVERVIEW

To meet the performance requirements of its target appli-

cations while maintaining low cost, the TM-1300 memory

subsystem couples substantial on-chip caches with a glue-

less memory interface through a unique internal bus or

data highway.

Dedicated instruction and data cache—The TM-1300 CPU is sup-

ported by separate, dedicated on-chip data and instruction caches that

employ a variety of techniques to improve cache hit ratios and thus

CPU performance.

The dual-ported data cache allows two simultaneous accesses. It is

non-blocking thus cache misses and CPU cache accesses can be han-

dled simultaneously. Early restart techniques reduce read-miss latency.

Background copyback reduces CPU stalls.

To reduce internal bus bandwidth requirements, instructions in main

memory and cache use a compressed format. Instructions are decom-

pressed in the instruction cache decompression unit before being

processed by the CPU.

To improve cache behavior and thus performance, both caches have a

locking mechanism. Cache coherency is maintained by software.

Glueless memory system interface—The TM-1300 couples main

memory to substantial on-chip caches through a glueless main memo-

ry interface (MMI). The MMI acts as the main memory controller

and programmable central arbiter that allocates memory bandwidth

for on-chip peripheral unit activities.

Support for a variety of memory configurations enables a wide variety

of TM-1300-based systems to be built. The MMI supports 16-Mbit

and 64-Mbit SDRAMs and provides sufficient drive capacity for an

up to 143-MHz memory system comprising 8-MB (one 2Mx32), 16-

MB (two 4Mx16 or two 2Mx32), or 32-MB (four 4Mx16 or four

2Mx32) memories. Larger memories (up to 64 MB) can be imple-

mented using lower memory system clock frequencies or external

buffers. Higher bandwidth SDRAM permits TM-1300 to use a nar-

rower and simpler interface than is required to achieve similar perfor-

mance with standard DRAM. Programmable speed ratios allow

SDRAM to have a different clock speed than the TM-1300 CPU.

HIGH-SPEED INTERNAL BUS (DATA HIGHWAY)

The TM-1300 CPU and processing units access external SDRAM

through the on-chip internal bus or data highway comprising separate

32-bit address and data buses. Handled by the MMI, programmable

bus arbitration enables the data highway to maintain real-time respon-

siveness in a variety of applications.

ROBUST SOFTWARE DEVELOPMENT ENVIRONMENT

The TriMedia SDE includes a full suite of system software tools to com-

pile and debug code, analyze and optimize performance, and simulate

execution for the TM-1300 processor. The SDE dramatically lowers

development costs, reduces time-to-market, and ensures code portability

to next generation architecture by enabling development of multimedia

applications entirely in the C and C++ programming languages.

The TriMedia SDE Version 2.0 also supports Metrowerks®

CodeWarrior® plug-ins. These plug-ins enable programmers to

develop C code for TriMedia processors using the popular Code-

Warrior Integrated Professional Development Environment (IDE).

TRIMEDIA APPLICATION LIBRARIES

Many TriMedia application libraries are available to accelerate product

development of common standard-compliant software algorithms used

in processing multimedia datastreams. These C-callable routines are

optimized for top performance on the TriMedia architecture.

Application libraries are available from Philips and third-party suppli-

ers and include functions such as MPEG-1 encode or decode, MPEG-

2 MP@ML decode, MPEG-2 1/2D1 MP@ML encode, H.320,

H.324, Dolby ProLogic or Dolby Digital (AC-3) decode, communica-

tions protocols, and many more. The TM-1300 can also support Java

applications with third-party Java virtual machine environments.

HOST-ASSISTED COPROCESSOR

SDRAM

CAMERA

AUDIO

PCI/XIO BUS

VCR

TV MONITOR

AUDIO

GRAPHICS

CARD

RGB IMAGE SEQUENCES

HOST CPU

MEMORY

STANDALONE

SDRAM

CAMERA

AUDIO

VCR

TV MONITOR

PERIPHERAL PERIPHERAL

AUDIO

PCI/XIO BUS

ROM/FLASH

BUS

ARBITER

TM-1300 is designed for use as the sole CPU in standalone systems

and as a coprocessor in a hosted or multiprocessor environment.

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