8405201XA 데이터 시트보기 (PDF) - Intersil
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8405201XA Datasheet PDF : 35 Pages
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80C86
AC Electrical Specifications
MINIMUM COMPLEXITY SYSTEM
VCC = 5.0V ±10%; TA = 0oC to +70oC (C80C86, C80C86-2)
VCC = 5.0V ±100%; TA = -40oC to +85oC (I80C86, I80C86-2)
VCC = 5.0V ±100%; TA = -55oC to +125oC (M80C86)
VCC = 5.0V ±5%; TA = -55oC to +125oC (M80C86-2)
SYMBOL
PARAMETER
80C86
MIN
MAX
80C86-2
MIN
MAX UNITS
TEST
CONDITIONS
TIMING REQUIREMENTS
(1) TCLCL Cycle Period
200
125
ns
(2) TCLCH CLK Low Time
118
68
ns
(3) TCHCL CLK High Time
69
44
ns
(4) TCH1CH2 CLK Rise Time
10
10
ns From 1.0V to 3.5V
(5) TCL2C1 CLK FaIl Time
10
10
ns From 3.5V to 1.0V
(6) TDVCL Data In Setup Time
30
20
ns
(7) TCLDX1 Data In Hold Time
10
10
ns
(8) TR1VCL RDY Setup Time into 82C84A
35
(Notes 7, 8)
35
ns
(9) TCLR1X RDY Hold Time into 82C84A
0
(Notes 7, 8)
0
ns
(10) TRYHCH READY Setup Time into 80C86
118
68
ns
(11) TCHRYX READY Hold Time into 80C86
30
20
ns
(12) TRYLCL READY Inactive to CLK (Note 9)
-8
-8
ns
(13) THVCH HOLD Setup Time
35
20
ns
(14) TINVCH lNTR, NMI, TEST Setup Time
30
(Note 8)
15
ns
(15) TILIH Input Rise Time (Except CLK)
15
15
ns From 0.8V to 2.0V
(16) TIHIL Input FaIl Time (Except CLK)
15
15
ns From 2.0V to 0.8V
TIMING RESPONSES
(17) TCLAV Address Valid Delay
(18) TCLAX Address Hold Time
(19) TCLAZ Address Float Delay
(20) TCHSZ Status Float Delay
(21) TCHSV Status Active Delay
(22) TLHLL ALE Width
(23) TCLLH ALE Active Delay
(24) TCHLL ALE Inactive Delay
10
10
TCLAX
10
TCLCH-20
110
10
60
10
80
TCLAX
50
80
50
110
10
60
TCLCH-10
80
50
85
55
ns CL = 100pF
ns CL = 100pF
ns CL = 100pF
ns CL = 100pF
ns CL = 100pF
ns CL = 100pF
ns CL = 100pF
ns CL = 100pF
3-157
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