92HD73C 데이터 시트보기 (PDF) - Integrated Device Technology
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92HD73C Datasheet PDF : 252 Pages
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92HD73C
SIX CHANNEL HD AUDIO CODEC, PREMIUM WLP 3/4 COMPLIANT
PC AUDIO
Note: Peak to peak jitter is currently limited to less than 4.5nS (half of the internal master clock cycle)
which does not meet the IEC-60958-3 0.05UI requirement at 192KHz.
The two SPDIF ouput converters can not be aligned in phase with the DACs. Even when attached to
the same stream, the two SPDIF output converters may be misaligned with respect to their frame
boundaries.
SPDIF Outputs on pins 48 and 40 are outlined in tables below. Pin 47 behavior table resides in the
EAPD section
AFG Power
State
D0-D3
D0
D1-D2
D3
RESET#
Asserted (Low)
De-Asserted (High)
De-Asserted (High)
De-Asserted (High)
De-Asserted (High)
De-Asserted (High)
De-Asserted (High)
De-Asserted (High)
Output Enable
Converter Dig
Enable
Stream ID
-
-
-
Disabled
-
-
Enabled
Disabled
-
Enabled
Enabled
0
Enabled
Enabled
1-15
Disabled
-
-
Enabled
-
-
-
-
-
Table 4. SPDIF OUT 0 (Pin 48) Behavior
Pin Behavior
Hi-Z (internal pull-down enabled)
immediately after power on,
otherwise the previous state is
retained until the rising edge of
RESET#
Hi-Z (internal pull-down enabled)
Active - Pin drives 0 (internal
pull-down NA)
Active - Pin drives SPDIF-format,
but data is zeroes (internal
pull-down NA)
Active - Pin drives SPDIFOut0
data (internal pull-down NA)
Hi-Z (internal pull-down enabled)
Active - Pin drives 0 (internal
pull-down NA)
Hi-Z (internal pull-down enabled)
AFG Power
State
RESET#
D0-D3
Asserted (Low)
D0-D3
De-Asserted (High)
GPIO 3
Enable
Output
Enable
Converter
Dig Enable
Stream ID
-
-
-
-
Enabled
-
-
-
Table 5. SPDIF OUT 1 (Pin 40) Behavior
Pin Behavior
Hi-Z (internal pull-down enabled)
immediately after power on,
otherwise the previous state is
retained until the rising edge of
RESET#
Active - Pin reflects GPIO7
configuration (internal pull-up
enabled)
15
SIX CHANNEL HD AUDIO CODEC, PREMIUM WLP 3/4 COMPLIANT
92HD73C
V 1.3 08/11
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