M38504M6-SP 데이터 시트보기 (PDF) - Renesas Electronics
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M38504M6-SP Datasheet PDF : 287 Pages
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APPENDIX
3.7 Machine instructions
Symbol
DEX
DEY
DIV
EOR
(Note 1)
INC
INX
Addressing mode
Function
Details
IMP
IMM
A
BIT, A
ZP
BIT, ZP
X←X–1
OP n # OP n # OP n # OP n # OP n # OP n #
This instruction subtracts one from the current CA 2 1
contents of X.
Y←Y–1
This instruction subtracts one from the current 88 2 1
contents of Y.
A ← (M(zz + X + 1),
M(zz + X )) / A
M(S) ← one's comple-
ment of Remainder
S←S–1
Divides the 16-bit data in M(zz+(X)) (low-order
byte) and M(zz+(X)+1) (high-order byte) by the
contents of A. The quotient is stored in A and
the one's complement of the remainder is
pushed onto the stack.
When T = 0
A ← A V– M
When T = 1
M(X) ← M(X) V– M
When T = 0, this instruction transfers the con-
tents of the M and A to the ALU which
performs a bit-wise Exclusive OR, and stores
the result in A.
When T = 1, the contents of M(X) and M are
transferred to the ALU, which performs a bit-
wise Exclusive OR and stores the results in
M(X). The contents of A remain unchanged,
but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
49 2 2
45 3 2
A ← A + 1 or
M←M+1
This instruction adds one to the contents of A
or M.
3A 2 1
E6 5 2
X←X+1
This instruction adds one to the contents of X. E8 2 1
INY
JMP
JSR
LDA
(Note 2)
LDM
LDX
LDY
Y←Y+1
This instruction adds one to the contents of Y. C8 2 1
If addressing mode is ABS
PCL ← ADL
PCH ← ADH
If addressing mode is IND
PCL ← M (ADH, ADL)
PCH ← M (ADH, ADL + 1)
If addressing mode is ZP, IND
PCL ← M(00, ADL)
PCH ← M(00, ADL + 1)
This instruction jumps to the address desig-
nated by the following three addressing
modes:
Absolute
Indirect Absolute
Zero Page Indirect Absolute
M(S) ← PCH
S←S–1
M(S) ← PCL
S←S–1
After executing the above,
if addressing mode is ABS,
PCL ← ADL
PCH ← ADH
if addressing mode is SP,
PCL ← ADL
PCH ← FF
If addressing mode is ZP, IND,
PCL ← M(00, ADL)
PCH ← M(00, ADL + 1)
This instruction stores the contents of the PC
in the stack, then jumps to the address desig-
nated by the following addressing modes:
Absolute
Special Page
Zero Page Indirect Absolute
When T = 0
A←M
When T = 1
M(X) ← M
When T = 0, this instruction transfers the con-
tents of M to A.
When T = 1, this instruction transfers the con-
tents of M to (M(X)). The contents of A remain
unchanged, but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
A9 2 2
M ← nn
This instruction loads the immediate value in
M.
X←M
This instruction loads the contents of M in X.
A2 2 2
Y←M
This instruction loads the contents of M in Y.
A0 2 2
A5 3 2
3C 4 3
A6 3 2
A4 3 2
3-72
3850 Group (Spec. H) User’s Manual
APPENDIX
3.7 Machine instructions
Addressing mode
Processor status register
ZP, X
ZP, Y
ABS ABS, X ABS, Y
IND ZP, IND IND, X IND, Y
REL
SP 7 6 5 4 3 2 1 0
OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # N V T B D I Z C
N• • • • • Z •
N• • • • • Z •
E2 16 2
••• •• •••
55 4 2
4D 4 3 5D 5 3 59 5 3
41 6 2 51 6 2
N• • • • • Z •
F6 6 2
EE 6 3 FE 7 3
4C 3 3
6C 5 3 B2 4 2
20 6 3
02 7 2
N• • • • • Z •
N• • • • • Z •
N• • • • • Z •
••• •• •••
22 5 2 • • • • • • • •
B5 4 2
AD 4 3 BD 5 3 B9 5 3
A1 6 2 B1 6 2
B6 4 2 AE 4 3
BE 5 3
B4 4 2
AC 4 3 BC 5 3
N• • • • • Z •
••• •• •••
N• • • • • Z •
N• • • • • Z •
3850 Group (Spec. H) User’s Manual
3-73
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