M38504M6-SP 데이터 시트보기 (PDF) - Renesas Electronics
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M38504M6-SP Datasheet PDF : 287 Pages
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APPENDIX
3.5 List of registers
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2
(ICON2 : address 3F16)
b
Name
Functions
0 Timer 1 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
1 Timer 2 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
2 Serial I/O1 receive 0 : Interrupt disabled
interrupt enable bit 1 : Interrupt enabled
3 Serial I/O1 transmit 0 : Interrupt disabled
interrupt enable bit 1 : Interrupt enabled
4 CNTR0 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
5 CNTR1 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
6 A-D converter
0 : Interrupt disabled
interrupt enable bit 1 : Interrupt enabled
7 Fix this bit to “0”.
Fig. 3.5.30 Structure of Interrupt control register 2
At reset R W
0
0
0
0
0
0
0
0
Flash memory control register
b7 b6 b5 b4 b3 b2 b1 b0
Flash memory control register
(FMCR : address 0FFE16)
b
Name
Functions
At reset R W
0 RY/BY status flag 0 : Busy (being written or
1
erased)
1 : Ready
1 CPU rewrite mode 0 : Normal mode (Software 0
select bit (Note 1)
commands invalid)
1 : CPU rewrite mode
(Software commands
acceptable)
2 CPU rewrite mode 0: Normal mode
0
entry flag
1: CPU rewrite mode
3 Flash memory reset 0: Normal operation
0
bit (Note 2)
1: Reset
4 User area/Boot
0: User ROM area
0
area selection bit 1: Boot ROM area
5 Nothing is arranged for these bits. When write,
6 set “0”. When these bits are read out, the
7 contents are undefined.
Undefined
Undefined
Undefined
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then
a “1” to it in succession.
2: Effective only when the CPU rewrite mode select bit = “1”. Set this
bit to “0” subsequently after setting it to “1” (reset).
Fig. 3.5.31 Structure of Flash memory control register
3850 Group (Spec. H) User’s Manual
3-65
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