CXB1563Q 데이터 시트보기 (PDF) - Sony Semiconductor
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CXB1563Q Datasheet PDF : 16 Pages
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CXB1563Q
• AC characteristics
(VCC = GND, VEE = –5V±10%, Ta = –40 to +85°C, VCC = VCCD, VCCDA, VCCA VEE = VEED, VEEA)
Item
Symbol
Conditions
Maximum input voltage amplitude Vmax Single-ended input
Amplifier gain
(in Limiting Amplifier)
Gv
Identification maximum voltage
amplitude of alarm level
VminA1
SW pad: Low,
single-ended input
VminA2
SW pad: Open High,
single-ended input
Hysteresis width
SD response assert time
SD response deassert time
∆P
Tas
Tdas
Low → High∗1
High → Low∗2
SD response assert time for alarm
level default
Tasd
Low → High∗3
SD response deassert time for
alarm level default
Tdasd High → Low∗4
Alarm setting level for default
Vdef
UP/DOWN pins; Open,
connect VEEI to VEE.
Propagation delay time
TPD
D to Q
Min. Typ. Max. Unit
1600
mVp-p
40
dB
20
mVp-p
50
4 67
dB
0
100
2.3
100
0
100 µs
2.3
100
6.6 8.0 9.3 mV
0.4 1.0 1.6 ns
Q/Q rise time
Q/Q fall time
SD/SD rise time
SD/SD fall time
Tr_Q
Tf_Q
Tr_SD
Tf_SD
RT1 = 50Ω, VT1 = –2V termination,
VEE = –5V, Ta = 0 to 85°C
20% to 80%
250
250
0.45
0.45
450
ps
450
1.6
ns
1.6
∗1 VUP – VDOWN = 100mV, Vin = 100mVp-p (single ended), SW pin: High
Peak hold capacitance (CAP2, CAP3 pins) of 470pF; connect VEEI to VEE.
∗2 VUP – VDOWN = 100mV, Vin = 1Vp-p (single ended), SW pin: High
Peak hold capacitance (CAP2, CAP3 pins) of 470pF; connect VEEI to VEE.
∗3 Vin = 50mVp-p (single ended), SW pin: Low
Peak hold capacitance (CAP2, CAP3 pins) of 470pF; connect VEEI to VEE.
∗4 Vin = 1Vp-p (single ended), SW pin: Low
Peak hold capacitance (CAP2, CAP3 pins) of 470pF; connect VEEI to VEE.
–7–
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