D8742 데이터 시트보기 (PDF) - Intel

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D8742

UNIVERSAL PERIPHERAL INTERFACE 8-BIT SLAVE MICROCONTROLLER

Intel 

8742

UPI-42 FEATURES

1 Two Data Bus Buffers one for input and one for

output This allows a much cleaner Master Slave

protocol

the IBF Status Bit A ‘‘0’’ written to P25 disables

the IBF pin (the pin remains low) This pin can be

used to indicate that the UPI is ready for data

290256 –3

2 8 Bits of Status

ST7 ST6 ST5 ST4 F1 F0 IBF OBF

D7 D6 D5 D4 D3 D2 D1 D0

ST4 – ST7 are user definable status bits These

bits are defined by the ‘‘MOV STS A’’ single byte

single cycle instruction Bits 4–7 of the acccumu-

lator are moved to bits 4–7 of the status register

Bits 0–3 of the status register are not affected

MOV STS A Op Code 90H

1 001000 0

D7

D0

3 RD and WR are edge triggered IBF OBF F1 and

INT change internally after the trailing edge of RD

or WR

290256 – 5

Data Bus Buffer Interrupt Capability

EN FLAGS Op Code 0F5H

1 111010 1

D7

D0

5 P26 and P27 are port pins or DMA handshake pins

for use with a DMA controller These pins default

to port pins on Reset

If the ‘‘EN DMA’’ instruction has been executed

P26 becomes the DRQ (DMA Request) pin A ‘‘1’’

written to P26 causes a DMA request (DRQ is acti-

vated) DRQ is deactivated by DACK#RD

DACK#WR or execution of the ‘‘EN DMA’’ in-

struction

If ‘‘EN DMA’’ has been executed P27 becomes

the DACK (DMA Acknowledge) pin This pin acts

as a chip select input for the Data Bus Buffer reg-

isters during DMA transfers

290256 –4

During the time that the host CPU is reading the

status register the 8742 is prevented from updat-

ing this register or is ‘‘locked out’’

4 P24 and P25 are port pins or Buffer Flag pins

which can be used to interrupt a master proces-

sor These pins default to port pins on Reset

If the ‘‘EN FLAGS’’ instruction has been execut-

ed P24 becomes the OBF (Output Buffer Full) pin

A ‘‘1’’ written to P24 enables the OBF pin (the pin

outputs the OBF Status Bit) A ‘‘0’’ written to P24

disables the OBF pin (the pin remains low) This

pin can be used to indicate that valid data is avail-

able from the UPI-41A (in Output Data Bus Buff-

er)

If ‘‘EN FLAGS’’ has been executed P25 becomes

the IBF (Input Buffer Full) pin A ‘‘1’’ written to P25

enables the IBF pin (the pin outputs the inverse of

290256 – 6

DMA Handshake Capability

EN DMA Op Code 0E5H

1 110010 1

D7

D0

6 The RESET input on the 8742 includes a 2-stage

synchronizer to support reliable reset operation

for 12 MHz operation

7 When EA is enabled on the 8742 the program

counter is placed on Port 1 and the lower three

bits of Port 2 (MSB e P22 LSB e P10) On the

8742 this information is multiplexed with PORT

DATA (see port timing diagrams at end of this

data sheet)

4

4

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