CXD2500BQ 데이터 시트보기 (PDF) - Sony Semiconductor

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CXD2500BQ

CD Digital Signal Processor

Sony Semiconductor 

CXD2500BQ

Note:

• The data at the 64-bit slot is output in 2’s complements on an LSB-first basis. The data at the 48-bit slot is

output in 2’s complements on an MSB-first basis.

• GTOP monitors the state of Frame Sync protection. (“H”: Sync protection window released)

• XUFG is a negative Frame Sync pulse obtained from the EFM signal before Frame Sync protection is

effected..

• XPLCK is an inversion of the EFM PLL clock. The PLL is designed so that the falling edge of XPLCK

coincides with a change point of the EFM signal.

• The GFS signal turns “H” upon coincidence between Frame Sync and the timing of interpolation protection.

• RFCK is a signal generated at 136-µs periods using a crystal oscillator.

• C2PO is a signal to indicate data error.

• XRAOF is a signal issued when a jitter margin of ±28F is exceeded by the 32K RAM.

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