CXD2500BQ 데이터 시트보기 (PDF) - Sony Semiconductor
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CXD2500BQ Datasheet PDF : 48 Pages
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CXD2500BQ
Pin Description
Pin
Symbol
No.
1 FOK
2 FSW
3 MON
4 MDP
5 MDS
6 LOCK
7
NC
8 VCOO
9 VCOI
10 TEST
11 PDO
12
VSS
13 NC
14 NC
15 NC
16 VPCO
17 VCKI
18 FILO
19 FILI
20 PCO
21 AVSS
22 CLTV
23 AVDD
24
RF
25 BIAS
26 ASYI
27 ASYO
28 ASYE
29 NC
30 PSSL
31 WDCK
32 LRCK
33
VDD
34 DA16
35 DA15
36 DA14
37 DA13
38 DA12
39 DA11
40 DA10
I/O
Description
I
Focus OK input. Used for SENS output and servo auto sequencer.
O
Z, 0 Output used to switch the spindle motor output filter.
O
1, 0 Output for spindle motor ON/OFF control
O 1, Z, 0 Output for spindle motor servo control
O 1, Z, 0 Output for spindle motor servo control
Output is “H” when the GFS signal sampled at 460 Hz is “H”. Output is
O
1, 0
“L” when the GFS signal is “L” 8 or more times in succession.
—
O
1, 0 Output of oscillation circuit for analog EFM PLL
I
Input to oscillation circuit for analog EFM PLL fLOCK=8.6436 MHz
I
Test. Normally at 0 V (GND).
O 1, Z, 0 Output of charge pump for analog EFM PLL
GND
—
—
—
O 1, Z, 0 Output of charge pump for vari-pitch PLL
I
Clock input from external VCO for vari-pitch control. fc center=16.9344 MHz.
O Analog Output of filter for master PLL (Slave=Digital PLL)
I
Input to filter for master PLL
O 1, Z, 0 Output of charge pump for master PLL
Analog GND
I
VCO control voltage input for master PLL
Analog power supply (+5 V)
I
EFM signal input
I
Asymmetry circuit constant current input
I
Asymmetry comparator circuit voltage input
O
1, 0 EFM full-swing output
I
Asymmetry circuit OFF at “L”. Asymmetry circuit ON at “H”.
—
Input used to switch the audio data output mode. “L” for serial output,
I
“H” for parallel output.
O
1, 0 D/A interface for 48-bit slot. Word clock f=2Fs
O
1, 0 D/A interface for 48-bit slot. LR clock f=Fs
Power supply (+5 V)
Outputs DA16 (MSB) when PSSL=1, or serial data from the 48-bit slot
O
1, 0
(2’s complements, MSB first) when PSSL=0.
O
1, 0 Outputs DA15 when PSSL=1, or bit clock from the 48-bit slot when PSSL=0.
Outputs DA14 when PSSL=1, or serial data from the 64-bit slot (2’s
O
1, 0
complements, LSB first) when PSSL=0.
O
1, 0 Outputs DA13 when PSSL=1, or bit clock from the 64-bit slot when PSSL=0.
O
1, 0 Outputs DA12 when PSSL=1, or LR clock from the 64-bit slot when PSSL=0.
O
1, 0 Outputs DA11 when PSSL=1, or GTOP when PSSL=0.
O
1, 0 Outputs DA10 when PSSL=1, or XUGF when PSSL=0.
—5—
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