PIC24HJ128GP202 데이터 시트보기 (PDF) - Microchip Technology
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PIC24HJ128GP202 Datasheet PDF : 357 Pages
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PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Type
Buffer
Type
PPS
Description
SCL1
I/O
SDA1
I/O
ASCL1
I/O
ASDA1
I/O
TMS
I
TCK
I
TDI
I
TDO
O
C1RX
I
C1TX
O
RTCC
O
CVREF
O
C1IN-
I
C1IN+
I
C1OUT
O
C2IN-
I
C2IN+
I
C2OUT
O
PMA0
I/O
PMA1
I/O
PMA2 -PMPA10 O
PMBE
O
PMCS1
O
PMD0-PMPD7 I/O
PMRD
O
PMWR
O
PGED1
I/O
PGEC1
I
PGED2
I/O
PGEC2
I
PGED3
I/O
PGEC3
I
ST
ST
ST
ST
ST
ST
ST
—
ST
—
—
ANA
ANA
ANA
—
ANA
ANA
—
TTL/ST
TTL/ST
—
—
—
TTL/ST
—
—
ST
ST
ST
ST
ST
ST
No Synchronous serial clock input/output for I2C1.
No Synchronous serial data input/output for I2C1.
No Alternate synchronous serial clock input/output for I2C1.
No Alternate synchronous serial data input/output for I2C1.
No JTAG Test mode select pin.
No JTAG test clock input pin.
No JTAG test data input pin.
No JTAG test data output pin.
Yes ECAN1 bus receive pin.
Yes ECAN1 bus transmit pin.
No Real-Time Clock Alarm Output.
No Comparator Voltage Reference Output.
No Comparator 1 Negative Input.
No Comparator 1 Positive Input.
Yes Comparator 1 Output.
No Comparator 2 Negative Input.
No Comparator 2 Positive Input.
Yes Comparator 2 Output.
No Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and
Output (Master modes).
No Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and
Output (Master modes).
No Parallel Master Port Address (Demultiplexed Master Modes).
No Parallel Master Port Byte Enable Strobe.
No Parallel Master Port Chip Select 1 Strobe.
No Parallel Master Port Data (Demultiplexed Master mode) or Address/
Data (Multiplexed Master modes).
No Parallel Master Port Read Strobe.
No Parallel Master Port Write Strobe.
No Data I/O pin for programming/debugging communication channel 1.
No Clock input pin for programming/debugging communication channel 1.
No Data I/O pin for programming/debugging communication channel 2.
No Clock input pin for programming/debugging communication channel 2.
No Data I/O pin for programming/debugging communication channel 3.
No Clock input pin for programming/debugging communication channel 3.
MCLR
I/P
ST
No Master Clear (Reset) input. This pin is an active-low Reset to the device.
AVDD
P
P
No Positive supply for analog modules. This pin must be connected at all
times.
AVSS
P
P
No Ground reference for analog modules.
VDD
P
—
No Positive supply for peripheral logic and I/O pins.
VCAP/VDDCORE
P
—
No CPU logic filter capacitor connection.
VSS
P
—
No Ground reference for logic and I/O pins.
VREF+
I Analog No Analog voltage reference (high) input.
VREF-
I Analog No Analog voltage reference (low) input.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
PPS = Peripheral Pin Select
Analog = Analog input
O = Output
TTL = TTL input buffer
P = Power
I = Input
DS70293D-page 14
Preliminary
© 2009 Microchip Technology Inc.
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