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AD5308ARU

2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP

Analog Devices 

AD5308/AD5318/AD5328

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

LDAC 1

SYNC 2

VDD 3

VOUTA 4

VOUTB 5

VOUTC 6

VOUTD 7

VREFABCD 8

AD5308/

AD5318/

AD5328

TOP VIEW

(Not to Scale)

16 SCLK

15 DIN

14 GND

13 VOUTH

12 VOUTG

11 VOUTF

10 VOUTE

9 VREFEFGH

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1

LDAC

This active low control input transfers the contents of the input registers to their respective DAC registers. Pulsing

this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simul-

taneous updates of all DAC outputs. Alternatively, this pin can be tied permanently low.

2

SYNC

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it

powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges

of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts as an

interrupt and the write sequence is ignored by the device.

3

VDD

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 μF

capacitor in parallel with a 0.1 μF capacitor to GND.

4

VOUTA

Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

5

VOUTB

Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

6

VOUTC

Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

7

VOUTD

Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

8

VREFABCD Reference Input Pin for DACs A, B, C, and D. It can be configured as a buffered, unbuffered, or VDD input to the four

DACs, depending on the state of the BUF and VDD control bits. It has an input range from 0.25 V to VDD in unbuffered

mode and from 1 V to VDD in buffered mode.

9

VREFEFGH Reference Input Pin for DACs E, F, G, and H. It can be configured as a buffered, unbuffered, or VDD input to the four

DACs, depending on the state of the BUF and VDD control bits. It has an input range from 0.25 V to VDD in unbuffered

mode and from 1 V to VDD in buffered mode.

10

VOUTE

Buffered Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.

11

VOUTF

Buffered Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.

12

VOUTG

Buffered Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.

13

VOUTH

Buffered Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.

14

GND

Ground Reference Point for All Circuitry on the Part.

15

DIN

Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the

serial clock input. The DIN input buffer is powered down after each write cycle.

16

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can

be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle.

Rev. F | Page 8 of 28

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