MAX1203ACAP(1998) 데이터 시트보기 (PDF) - Maxim Integrated
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MAX1203ACAP Datasheet PDF : 24 Pages
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5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
CS
SCLK
1 2 345678
DIN
SSTRB
DOUT
ADC STATE
SEL2 SEL1 SEL0
UNI/
BIP
SGL/
DIF
PD1
PD0
START
tCONV
ACQUISITION CONVERSION
IDLE
1.5µs
(SCLK = 2MHz)
10µs MAX
9 10 11 12
B11
MSB
B10
B9
Figure 9. Internal Clock Mode Timing
18 19 20 21 22 23 24
B2
B1
B0
LSB
FILLED WITH
ZEROS
IDLE
CS • • •
SSTRB • • •
SCLK • • •
tCONV
tCSH
tSSTRB
tCSS
tSCK
PD0 CLOCK IN
NOTE: KEEP SCLK LOW DURING CONVERSION FOR BEST NOISE PERFORMANCE.
Figure 10. Internal Clock Mode SSTRB Detailed Timing
conversion is started. Pulling CS high prevents data from
being clocked into the MAX1202/MAX1203 and three-
states DOUT, but it does not adversely affect an internal
clock mode conversion already in progress. When
internal clock mode is selected, SSTRB does not go into
a high-impedance state when CS goes high.
Figure 10 shows SSTRB timing in internal clock mode.
Data can be shifted in and out of the MAX1202/MAX1203
at clock rates up to 2.0MHz, if tACQ is kept above 1.5µs.
Data Framing
CS’s falling edge does not start a conversion on the
MAX1202/MAX1203. The first logic high clocked into DIN
is interpreted as a start bit and defines the first bit of the
control byte. A conversion starts on SCLK’s falling edge
after the eighth bit of the control byte (the PD0 bit) is
clocked into DIN. The start bit is defined as one of the
following:
The first high bit clocked into DIN with CS low any-
time the converter is idle (e.g., after VDD is applied).
or
The first high bit clocked into DIN after bit 5 (B5) of a
conversion in progress appears at DOUT.
If a falling edge on CS forces a start bit before B5
becomes available, the current conversion is termi-
nated and a new one started. Thus, the fastest the
MAX1202/MAX1203 can run is 15 clocks/conversion.
______________________________________________________________________________________ 15
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