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74LV595 Datasheet PDF : 20 Pages
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NXP Semiconductors
74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13.
Symbol Parameter
Conditions
−40 °C to +85 °C
Min Typ[1] Max
fmax
maximum
frequency
SHCP or STCP; see Figure 8
and Figure 9
VCC = 2.0 V
14.0 40.0
-
VCC = 2.7 V
19.0 58.0
-
VCC = 3.3 V; CL = 15 pF
-
77
-
VCC = 3.0 V to 3.6 V
[3] 24.0 70.0
-
CPD
power dissipation VI = GND to VCC; VCC = 3.0 V [7] -
115
-
capacitance
−40 °C to +125 °C Unit
Min
Max
12
-
MHz
16
-
MHz
-
-
MHz
20
-
MHz
-
-
pF
[1] Typical values are measured at Tamb = 25 °C.
[2] tpd is the same as tPLH and tPHL.
[3] Typical value measured at VCC = 3.3 V.
[4] ten is the same as tPZH and tPZL.
[5] tdis is the same as tPHZ and tPLZ.
[6] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[7] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
12. Waveforms
VI
SHCP input
GND
VOH
Q7S output
VOL
1/ fmax
VM
tW
t PLH
VM
t PHL
mna557
Fig 8.
Measurement points are given in Table 8.
VOL and VOH are typical output voltage drops that occur with the output load.
The shift clock (SHCP) to serial data output (Q7S) propagation delays, the shift clock pulse width and
maximum shift clock frequency
74LV595_3
Product data sheet
Rev. 03 — 21 April 2009
© NXP B.V. 2009. All rights reserved.
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