74ALVT16827(2018) 데이터 시트보기 (PDF) - NXP Semiconductors.
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74ALVT16827 Datasheet PDF : 14 Pages
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Nexperia
74ALVT16827
20-bit buffer/line driver; non-inverting; 3-state
VI 90 %
tW
negative
pulse
VM
10 %
0V
tf
VI
positive
pulse
tr
90 %
VM
10 %
0V
tW
VI
G
VCC
VO
DUT
RT
VM
tr
tf
VM
VEXT
RL
CL
RL
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Test data is given in Table 9.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Figure 7. Test circuit for measuring switching times
Table 9. Test data
Input
VI
fi
3.0 V or VCC
≤ 10 MHz
whichever is less
tW
500 ns
tr, tf
≤ 2.5 ns
Load
CL
50 pF
RL
500 Ω
VEXT
tPHZ, tPZH
GND
tPLZ, tPZL
tPLH, tPHL
6 V or VCC x 2 open
74ALVT16827
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 24 January 2018
© Nexperia B.V. 2018. All rights reserved.
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