MCIMX283DVM4B(2012) 데이터 시트보기 (PDF) - Freescale Semiconductor

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MCIMX283DVM4B
(Rev.:2012)

i.MX28 Applications Processors Data Sheet for Consumer Products

Freescale Semiconductor 

Features

Table 4. i.MX28 Digital and Analog Modules (continued)

Block

Mnemonic

RTC

SAIF(2)

SPDIF

SSP(4)

TIMROT

USBOTG

USBHOST

USBPHY

Block Name Subsystem

Brief Description

Real-time

Clocks

clock, alarm,

watchdog

Serial audio Connectivity

interface

peripherals

SPDIF

Connectivity

peripherals

Synchronous Connectivity

serial port peripherals

Timers and

Rotary

Decoder

Timer

peripherals

High-speed

USB

on-the-go

Connectivity

peripherals

Integrated

USB PHY

Connectivity

peripherals

The real-time clock (RTC) and alarm share a one-second pulse time domain.

The watchdog reset and millisecond counter run on a one-millisecond time

domain. The RTC, alarm, and persistent bits reside in a special power

domain (crystal domain) that remains powered up even when the rest of the

chip is in its powered-down state.

SAIF provides a half-duplex serial port for communication with a variety of

serial devices, including industry-standard codecs and DSPs. It supports a

continuous range of sample rates from 8 kHz–192 kHz using a

high-resolution fractional divider driven by the PLL. Samples are transferred

to/from the FIFO through the APBX DMA interface, a FIFO service interrupt,

or software polling.

The Sony-Philips Digital Interface Format (SPDIF) transmitter module

transmits data according to the SPDIF digital audio interface standard

(IEC-60958).

The synchronous serial port is a flexible interface for inter-IC and removable

media control and communication. The SSP supports master operation of

SPI, Texas Instruments SSI; 1-bit, 4-bit, and 8-bit SD/SDIO/MMC and 1-bit

and 4-bit MS modes.

The SPI mode has enhancements to support 1-bit legacy MMC cards. SPI

master dual (2-bit) and quad (4-bit) mode reads are also supported. The SSP

also supports slave operation for the SPI and SSI modes. The SSP has a

dedicated DMA channel in the bridge and can also be controlled directly by

the CPU through PIO registers. Each of the four SSP modules is

independent of the other and can have separate SSPCLK frequencies.

This module implements four timers and a rotary decoder. The timers and

decoder can take their inputs from any of the pins defined for PWM, rotary

encoders, or certain divisions from the 32-kHz clock input. Thus, the PWM

pins can be inputs or outputs, depending on the application.

The USB module provides high-performance USB On-The-Go (OTG) and

host functionality (up to 480 Mbps), compliant with the USB 2.0 specification

and the OTG supplement. The module has DMA capabilities for handling

data transfer between internal buffers and system memory.

When the OTG controller works in device mode, it can only work in FS or HS

mode. Two USB2.0 PHYs are also integrated (one for the OTG port, another

for the host port.)

The integrated USB 2.0 PHY macrocells are capable of connecting to USB

host/device systems at the USB low-speed (LS) rate of 1.5 Mbps, full-speed

(FS) rate of 12 Mbps or at the USB 2.0 high-speed (HS) rate of 480 Mbps.

The integrated PHYs provide a standard UTM interface. The USB_DP and

USB_DN pins connect directly to a USB connector.

i.MX28 Applications Processors for Consumer Products, Rev. 3

10

Freescale Semiconductor

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