M66273FP 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC
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M66273FP Datasheet PDF : 34 Pages
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Ver.3.1 Dec,1999
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
OUTLINE
The M66273 is a graphic display only controller for displaying a dot
matrix type STN-LCD.
· LCD display mode
It is capable of displaying six types of LCD by combining the panel
configuration, binary/gray scale, LCD display data bus width.
Display Panel
Binary/ LCD display Displayable LCD
mode configuration gray scale data
size
1
4bit
Equivalent to 640
2
Single
Binary
8bit
x 240
3
scan
4bit
Gray scale
Equivalent to 320
4
8bit
x 240
5
Dual
Binary
4bit
Equivalent to 320 x
240 x 2 screens
6
scan Gray scale
4bit
Equivalent to 320 x
120 x 2 screens
· Control register
When accessing the control register from MPU, use pins IOCS,
LWR, RD, A<7:0> and D<7:0>, or MCS, LWR, RD,A<14:0> and
D<7:0> (However, use D<15:0> only when 16-bit MPU controls the
LCD module built-in support function.)
Refer to Table-1, setting of control input.
The IC contains the following registers as control registers.
Operation control
R1 to R11
Supporting LCD module built-in type R12 to 14 or R15 to 16
Gray scale pattern table
R17 to R80
· VRAM
This IC has a built-in 19200-byte VRAM which is equivalent to two
screens of 320 x 240 dots LCD.
When accessing VRAM from MPU, use pins MCS, HWR, LWR,
RD, BHE, A<14:0> and D<15:0>.
Use of MPUSEL input can support both 8/16 bit MPU.
Refer to table-2 to 6, VRAM specifications for 8/16 bit MPU and input
setting in access.
The VRAM address settable range is restricted depending on the
panel configuration, as follows.
VRAM address settable range
· When single scan mode
·A<14:0>=0000 to 4AFFH --- 19200 byte
0000H
VRAM
4AFFH
· When dual scan mode
·For the 1st screen --- A<14:0>=0000 to 257F H --- 9600 byte
·For the 2nd screen --- A<14:0>=2580 to 4AFFH --- 9600 byte
0000H
VRAM for the 1st screen
257FH
2580H
VRAM for the 2nd screen
4AFFH
· Cycle steal system
Cycle steal system is interact method of transforming display data for
LCD from VRAM and accessing VRAM from MPU on the basic
cycle (MAINCLK) of internal operation.
Basic timing is two clocks of MAINCLK, and assign first clock to the
access from MPU to VRAM and second clock to the transfer of
display data from VRAM to LCD.
In accessing VRAM from MPU, output WAIT. In case of fixed
WAITCNT input, change WAIT to "L" at the timing of the falling edge
of overlapping with MCS and RD or LWR / HWR,and in case of
using WAITCNT input, change WAIT to "L" at the timing of the falling
edge of WAITCNT on MCS="L", And return to "H" at synchronizing
with rising edge of M PUCLK after internal processing.
For the cycle steal system, this IC provides a cycle steal control
function to improve data transfer efficiency in a line. This func-tion
gains access with the cycle steal system by taking WAIT for MPU
during the display term with necessity for the display data transfer
from built-in VRAM to LCD. On the other side, it does not output
WAIT for keeping throughput of MPU during horizontal synchronous
term (idle running term) with no necessity for the display data
transfer from VRAM to LCD side.
In detail,refer to "Description of cycle steal".
· Output to LCD side
LCD display data VD<7:0> is output in parallel per 4 bits or 8 bits in
synchronization with the rising edge of CP.
Pin VD<n:0> differs depending on the display mode.
Single scan
4-bit transfer
8-bit transfer
VD<3:0>
VD<7:0>
Dual scan
4-bit transfer
VD<7:4>
VD<3:0>
Display mode 1 3
24
56
When display data for a line has been sent, LP outputs data in
synchronization with the falling edge of MAINCLK.
The IC enables adjustment to an optimum value of the frame
frequency as requested from the LCD PANEL side by adjusting pulse
width of LP with the LPW register value.
FLM is output when the display data for the first line has been sent.
M output is an LCD alternating signal for driving LCD with alternating
current.
M output cycles can be set in lines with the M output cycle variable
register and is available to prevent LCD from deterioration.
· Gray scale display function
Gray scale display can assign 2-bit VRAM data to a picture element
of LCD display to show the display density at four levels.
Gray scale display pattern tables 0 and 1 (4 x 4 matrix x 16 patterns x
2 medium gray scale), consisting of SRAM of 64 bytes in total, can
set any gray scale display pattern.
In detail,refer to "Description of gray scale function".
· Application to reflective color type LCD
The above gradation display function is available to control about four
display colors on the reflective color type LCD with ECB (Electrically
Controlled Birefringence).
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