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M66273FP

LCD CONTROLLER with VRAM

MITSUBISHI ELECTRIC  

MITSUBISHI <DIGITAL ASSP>

M66273FP

Ver.3.1 Dec,1999

LCD CONTROLLER with VRAM

PIN DESCRIPTIONS

Item

Input/

Pin name Output

Function

D<15:0>

Input/

Output

MPU data bus

When selecting 8 bit MPU by MPUSEL input, connect D<15:8> to "VDD" or "VSS".

A<14:0>

Input

MPU address bus

When selecting 8-bit MPU, use A<14:0>.

When selecting 16-bit MPU, use A<14:1> as a address bus. By combining A<0> and BHE, access to

internal VRAM can be gained.

When driving two screens (dual scan mode), notice that the allowable setup range of VRAM address

is restricted. When IOCS control use A <7:0>, and MCS control use A <14:0> for selecting address of

control register.

IOCS

Chip select input of control register

Input When this pin is "L", select the internal control register. Assign to I/O space of MPU.

MCS Input

HWR Input

LWR Input

MPU

RD

Input

interface MPUSEL Input

RESET Input

MPUCLK Input

BHE Input

WAITCNT Input

Chip select input of VRAM / control register

When this pin is "L", select the internal VRAM. Assign to memory space of MPU.

And this pin can for chip select of control register.

In detail, refer to "COMBINATIONS OF CONTROL INPUT PINS ON THE MPU INTERFACE" and "CONTROL

REGISTER".

High-Write strobe input

When this pin is "L", write data to the internal VRAM. HWR is valid only in using 16-bit MPU

controlled byte access by LWR and HWR.

Low-Write strobe input

When this pin is "L", write data to the internal control register or VRAM.

Read strobe input

When this pin is "L", read data from the internal control register or VRAM.

8/16-bit MPU select input

According to MPU, set "VSS" for 8-bit MPU and set "VDD" for 16-bit MPU.

Reset input

Use reset signal of MPU. When this pin is "L", initialize (reset) all internal control registers and

counters.

MPU clock

Input system clock output from MPU.

Bus-High-Enable input

This pin is valid when using 16-bit MPU controlling byte access with A<0> and BHE.

Connect to "VDD" to select 8-bit MPU.

Wait control input

This pin is used for controlling WAIT output timing when requested access from MPU to VRAM.

Use this pin, when it is necessary to output WAIT earlier than the timing of falling edge of overlapping with

MCS and RD or LWR and HWR.

And then connect AS, ALE or etc of MPU.

Connect WAITCNT to "VDD" or "VSS", when it is necessary to output WAIT at the timing of falling edge of

overlapping with MCS and RD or LWR and HWR.

Number

of pins

16

15

1

1

1

1

1

1

1

1

1

1

WAIT output for MPU

This signal makes WAIT for MPU. In case of fixed WAITCNT input("VSS" or "VDD" )change WAIT to

"L" at the timing of falling edge of overlapping with MCS and RD or LWR and HWR. And in case of

WAIT Output using WAITCNT input, change WAIT to "L" at timing of falling edge of WAITCNT on MCS = "L".

1

And WAIT output return to "H" at synchronization with the rising edge of MPUCLK after internal

processing. (Output WAIT only when requested access from MPU to VRAM is gained during cycle

steal access.)

Cycle Steal Enable output

CSE Output State output of internal cycle steal access.

1

3

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