ADV7480BBCZ-RL 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
일치하는 목록
ADV7480BBCZ-RL Datasheet PDF : 19 Pages
| |||
ADV7480
Data Sheet
TIMING SPECIFICATIONS
AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V,
DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted.
Table 3.
Parameter
Symbol Test Conditions/Comments
Min
CLOCK AND CRYSTAL
Nominal Frequency1
Frequency Stability1
Input LLC Clock Frequency Range2,3
DVDDIO = 3.14 V to 3.46 V
13.5
Output LLC Clock Frequency Range2,3
DVDDIO = 3.14 V to 3.46 V
13.5
SPI_SCLK Frequency3
I2S_SCLK Frequency3
I2S_MCLK Frequency3
I2C PORT
SCLK Frequency
SCLK Minimum Pulse Width High
t1
0.6
SCLK Minimum Pulse Width Low
t2
1.3
Hold Time (Start Condition)
t3
0.6
Setup Time (Start Condition)
t4
0.6
SDATA Setup Time
t5
100
SCLK and SDATA Rise Times
t6
SCLK and SDATA Fall Times
t7
Setup Time (Stop Condition)
t8
SPI PORT
Slave Mode
SPI_CS Falling Edge to SPI_SCLK t9
Active Edge
SPI_SCLK active edge (rising or falling 35
edge) depends on the values of CPHA
and CPOL
SPI_SCLK Active Edge to SPI_CS t10
Rising Edge
SPI_SCLK active edge (rising or falling 35
edge) depends on the values of CPHA
and CPOL
SPI_CS Pulse Width
t11
50
SPI_SCLK High Time3
t12
45
SPI_SCLK Low Time3
t12
45
SPI_MOSI Setup Time
t13
SPI Mode 0, SPI Mode 3
0
SPI_MOSI Hold Time
t14
SPI Mode 0, SPI Mode 3
35
SPI_SCLK Falling Edge to SPI_MISO t15
Start of Data Invalid3
SPI Mode 0, SPI Mode 3
SPI_SCLK Falling Edge to SPI_MISO t16
End of Data Invalid3
SPI Mode 0, SPI Mode 3
SPI_MOSI Setup Time
t17
SPI Mode 1, SPI Mode 2
0
SPI_MOSI Hold Time
t18
SPI Mode 1, SPI Mode 2
35
SPI_SCLK Rising Edge to SPI_MISO t19
Start of Data Invalid
SPI Mode 1, SPI Mode 2
SPI_SCLK Rising Edge to SPI_MISO t20
End of Data Invalid
SPI Mode 1, SPI Mode 2
RESET FEATURE
RESET Pulse Width1
5
Typ
Max
28.63636
±50
148.5
148.5
10
12.288
24.576
400
300
300
0.6
Unit
MHz
ppm
MHz
MHz
MHz
MHz
MHz
kHz
µs
µs
µs
µs
ns
ns
ns
µs
ns
ns
ns
55
% duty
cycle
55
% duty
cycle
ns
ns
50
ns
50
ns
ns
ns
35
ns
35
ns
ms
Rev. 0 | Page 8 of 19
Share Link: 