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ADV7480BBCZ-RL

Dual Mode HDMI/MHL Receiver

Analog Devices 

Data Sheet

Dual Mode HDMI/MHL Receiver

ADV7480

FEATURES

Mobile High-Definition Link (MHL) capable receiver

High-bandwidth Digital Content Protection (HDCP)

authentication and decryption support

75 MHz maximum pixel clock frequency, allowing HDTV

formats up to 720p/1080i at 60 Hz

24 bits per pixel mode supported

HDCP repeater support, up to 25 KSVs supported

Adaptive TMDS equalizer

High-Definition Multimedia Interface (HDMI) capable

receiver

HDCP authentication and decryption support

162 MHz maximum pixel clock frequency, allowing HDTV

formats up to 1080p and display resolutions up to UXGA

(1600 × 1200 at 60 Hz)

HDCP repeater support, up to 25 KSVs supported

Integrated CEC controller, CEC 1.4 compatible

Adaptive TMDS equalizer

5 V detect and Hot Plug assert

Component video processor

Any-to-any 3 × 3 color space conversion (CSC) matrix

Contrast/brightness/hue/saturation video adjustment

Timing adjustments controls for horizontal sync

(HS)/vertical sync (VS)/data enable (DE) timing

Video mute function

Serial digital audio output interface

HDMI/MHL audio extraction support

Advanced audio muting feature

I2S-compatible, left justified and right justified audio

output modes

8-channel TDM output mode available

Mobile Industry Processor Interface (MIPI) Camera Serial

Interface 2 (CSI-2) transmitter

4-lane transmitter with 4 lanes, 2 lanes, and 1 lane muxing

options for HDMI/MHL/digital input port sources

8-bit digital input/output port

General

2-wire serial microprocessor unit (MPU) interface (I2C

compatible)

−40°C to +85°C temperature grade

100-ball, 9 mm × 9 mm, RoHS-compliant CSP_BGA package

Qualified for automotive applications

APPLICATIONS

Portable devices

Automotive infotainment (head unit and rear seat

entertainment systems)

HDMI repeaters and video switches

RXCP/RXCN

RX0P/RX0N

RX1P/RX1N

RX2P/RX2N

DDC_SCL/

CD_PULLU P

DDC_SD A

HPD/CBUS

CD_SENSE

CEC

RX_5V/VBUS

VBUS_EN

LLC

P0 TO P7

FUNCTIONAL BLOCK DIAGRAM

ADV7480

SPI

SLAVE

MHL_SENSE

CBUS

DDC

HDMI/MHL

RECEIVER

CEC

HPD

EDID RAM

HDCP

8-BIT TTL

INPUT/OUTPUT

AUDIO

PROCESSOR

COMPONENT

PROCESSOR

(CP)

I2C

SLAVE

INTERRUPTS

CONTROLLER

AUDIO

OUTPUT

FORMATTER

4-LANE

MIPI CSI-2

TRANSMITTER

SPI_MISO

SPI_MOSI

SPI_SCLK

SPI_CS

ALSB

SCLK

SDATA

INTRQ1 TO

INTRQ3

I2S_MCLK

I2S_LRCLK

I2S_SCLK

I2S_SDATA

CLKAP/CLKAN

DA0P/DA0N TO

DA3P/DA3N

Figure 1.

Rev. 0

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