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ADV7480WBBCZ

Dual Mode HDMI/MHL Receiver

Analog Devices 

Data Sheet

ADV7480

THEORY OF OPERATION

COMBINED HDMI/MHL RECEIVER

The ADV7480 features a combined HDMI/MHL receiver. This

single receiver port is capable of accepting both HDMI and

MHL electrical signals. Automatic detection between HDMI

and MHL is achieved by using cable impedance detection

through the CD_SENSE pin.

Both MHL and HDMI interfaces of the ADV7480 allow

authentication of a video receiver, decryption of encoded data at

the receiver, and renewability of that authentication during

transmission, as specified by the HDCP 1.4 protocol.

Dual extended display identification data (EDID) support is

provided via an on-chip 512-byte EDID RAM. The EDID RAM

must be programmed at power-up. It can be configured as two

256-byte EDIDs for dual mode operation (one 256-byte EDID

for the HDMI receiver, and one 256-byte EDID for the MHL

receiver), or as a single 512-byte EDID for single mode operation.

The ADV7480 has a synchronization regeneration block used to

regenerate the data enable (DE) signal based on the measurement

of the video format being displayed and to filter the horizontal

and vertical synchronization signals to prevent glitches.

The combined HDMI/MHL receiver also supports TMDS error

reduction coding, 4-bit (TERC4) error detection, used for the

detection of corrupted HDMI or MHL packets.

MHL RECEIVER

The MHL receiver supports video formats ranging from 480i to

720p/1080i, and display resolutions from VGA (640 × 480 at

60 Hz) to XGA (1024 × 768 at 60 Hz).

The MHL receiver allows programmable equalization of the

MHL data signals. This equalization compensates for the high

frequency losses inherent in MHL cabling, especially at longer

lengths and higher frequencies. The receiver is capable of

equalizing for cable lengths of up to 2 meters to achieve robust

receiver performance.

The MHL receiver includes the following pins:

• RX0N and RX0P. In MHL mode, this differential pair

receives the data transmitted as a differential signal, and

the clock transmitted on the common mode.

• HPD/CBUS. In MHL mode, this pin is used for CBUS

communication.

• VBUS_EN. This pin provides an enable signal for an

external source providing 5 V of power to the MHL source

on VBUS.

• RX_5V/VBUS. In MHL mode, this pin is an input

monitoring the VBUS signal provided by an external

source enabled by VBUS_EN.

• CD_SENSE. This pin detects whether the signals provided

to the HDMI/MHL receiver are HDMI signals or MHL

signals. A high level indicates MHL, and a low level

indicates HDMI.

The implementation of the MSC commands by the system

processor can be handled either through the I2C bus, or via a

dedicated SPI bus. A dedicated interrupt pin (INTRQ3) is

available to indicate that events related to the CBUS have occurred.

The main MHL receiver features include

• Support for a pixel clock up to 75 MHz in 24-bit mode,

allowing support for video formats up to 720p/1080i and

display resolutions up to XGA in either RGB, YCbCr 4:4:4,

or YCbCr 4:2:2 formats.

• Integrated fully adaptive equalizer for cable lengths up to

2 meters.

• HDCP 1.4 support.

• Internal HDCP keys.

• HDCP repeater support, up to 25 key selection vectors

(KSVs) supported.

• Pulse code modulation (PCM) audio packet support.

• Support for 8-channel TDM output data up to 48 kHz.

• Repeater support.

• Internal EDID RAM (512-byte for single mode, and

256-byte for dual mode operation).

• Scratchpad register support with a size of 64 bytes.

HDMI RECEIVER

The HDMI receiver supports video formats ranging from 480i

to 1080p, and display resolutions from VGA (640 × 480 at

60 Hz) to UXGA (1600 × 1200 at 60 Hz).

The HDMI receiver allows programmable equalization of the

HDMI data signals. This equalization compensates for the high

frequency losses inherent in HDMI and DVI cabling, especially

at longer lengths and higher frequencies. The receiver is capable

of equalizing for cable lengths up to 30 meters to achieve robust

receiver performance.

The main HDMI receiver features include

• 162.0 MHz (UXGA at 24 BPP) maximum TMDS clock

frequency.

• Integrated fully adaptive equalizer for cable lengths up to

30 meters.

• HDCP 1.4 support.

• Internal HDCP keys.

• HDCP repeater support, up to 25 key selection vectors

(KSVs) supported.

• PCM audio packet support.

• Support for 8-channel TDM output data up to 48 kHz.

• Repeater support.

• Internal EDID RAM (512-byte for single mode, and

256-byte for dual mode operation).

• Hot Plug assert output pin (HPD/CBUS).

• CEC controller.

Rev. 0 | Page 17 of 19

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