CY7C1427KV18 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1427KV18 Datasheet PDF : 32 Pages
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CY7C1416KV18, CY7C1427KV18
CY7C1418KV18, CY7C1420KV18
Pin Definitions (continued)
Pin Name
I/O
Pin Description
CQ
Output clock CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock for
output data (C) of the DDR II. In the single clock mode, CQ is generated with respect to K. The timing for
the echo clocks is shown in the AC Timing table.
CQ
Output clock CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock for
output data (C) of the DDR II. In the single clock mode, CQ is generated with respect to K. The timing for
the echo clocks is shown in the AC Timing table.
ZQ
Input
Output impedance matching input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
DOFF
Input
PLL turn off active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing
in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
is connected to a pull-up through a 10 K or less pull-up resistor. The device behaves in DDR-I mode
when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with DDR-I timing.
TDO
Output TDO for JTAG.
TCK
Input
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG.
TMS
Input
TMS pin for JTAG.
NC
N/A
Not connected to the die. Can be tied to any voltage level.
NC/72M
Input
Not connected to the die. Can be tied to any voltage level.
NC/144M
Input
Not connected to the die. Can be tied to any voltage level.
NC/288M
Input
Not connected to the die. Can be tied to any voltage level.
VREF
Input- Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC
reference measurement points.
VDD
VSS
VDDQ
Power supply Power supply Inputs to the core of the device.
Ground Ground for the device.
Power supply Power supply inputs for the outputs of the device.
Document Number: 001-57827 Rev. *B
Page 8 of 32
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