CY7C1427KV18 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1427KV18 Datasheet PDF : 32 Pages
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CY7C1416KV18, CY7C1427KV18
CY7C1418KV18, CY7C1420KV18
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to allow the SRAM to adjust its output
driver impedance. The value of RQ must be 5 × the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175 and 350 , with VDDQ = 1.5 V. The
output impedance is adjusted every 1024 cycles upon power-up
to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the DDR II to simplify data capture
on high speed systems. Two echo clocks are generated by the
DDR II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free running clocks and are
synchronized to the output clock of the DDR II. In single clock
mode, CQ is generated with respect to K and CQ is generated
with respect to K. The timing for the echo clocks is shown in the
Switching Characteristics on page 25.
PLL
These chips use a PLL which is designed to function between
120 MHz and the specified maximum clock frequency. During
power up, when the DOFF is tied HIGH, the PLL is locked after
20 s of stable clock. The PLL can also be reset by slowing or
stopping the input clock K and K for a minimum of 30 ns.
However, it is not necessary to reset the PLL to lock to the
desired frequency. The PLL automatically locks 20 s after a
stable clock is presented. The PLL may be disabled by applying
ground to the DOFF pin. When the PLL is turned off, the device
behaves in DDR-I mode (with one cycle latency and a longer
access time).
Application Example
Figure 1 shows two DDR II used in an application.
Figure 1. Application Example
SRAM#1
ZQ R = 250ohms
DQ
CQ/CQ#
A LD# R/W# C C# K K#
DQ
BUS
Addresses
MASTER Cycle Start#
(CPU
or
R/W#
Return CLK
ASIC) Source CLK
Return CLK#
Source CLK#
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2
Vterm = 0.75V
R = 50ohms
Vterm = 0.75V
SRAM#2
ZQ R = 250ohms
DQ
CQ/CQ#
A LD# R/W# C C# K K#
Document Number: 001-57827 Rev. *B
Page 10 of 32
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