LH543620 데이터 시트보기 (PDF) - Sharp Electronics

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LH543620

1024 × 36 Synchronous FIFO

Sharp Electronics 

LH543620

1024 × 36 Synchronous FIFO

Control Register (See Figure 7)

After reset, the control register’s value is 1. This sets

the following conditions:

Odd parity

Disabling parity generation (parity check is active).

AF, HF, AE flags are asynchronous.

OE signal does not control the Read pointer.

Read/Write Resource Register Mode

It is possible to write to the resource registers from

either the Input Port or the Output Port. Reading from the

resource register is possible only from the Output Port.

The source port for the write operation is determined by

the control signal CAPR.

Input Port:

Data from the Input Port is written to a resource register

when:

the value of the input-address field, ADI, selects the

register (see Table 1)

CAPR is LOW

The operation is enabled by ADI[2:0] and synchronized

to CKI.

Output Port:

Data from the Output Port is written to a resource

register when:

the value of the output-address field, ADO, selects the

register (see Table 4)

CAPR is HIGH

OE is HIGH

NOTE: ADI[2:0] should remain stable whenever data is

coming in from the output port.

Data is read from a resource register to the Output Port

when:

the value of the output-address field, ADO, selects the

register (see Table 4)

OE is LOW

Both operations are enabled by ADO[2:0] and are

synchronous to CKO.

MAILBOX

The mailbox mechanism includes:

One 36-bit data register.

Two status flags:

– MFF Mailbox Full Flag

– MEF Mailbox Empty Flag

654 3 210

0 EVEN PARITY

1 ODD PARITY

0 PARITY GENERATION IS DISABLED

1 PARITY GENERATION IS ENABLED

0 AE ASYNCHRONOUS

1 AE SYNCHRONOUS TO CKO

0 HF ASYNCHRONOUS

1 HF SYNCHRONOUS TO CKO

2 OR 3 HF SYNCHRONOUS TO CKI

0 AF ASYNCHRONOUS

1 AF SYNCHRONOUS TO CKI

0 OE DOES NOT CONTROL THE READ POINTER

1 OE CONTROLS THE READ POINTER

Figure 7. LH543620 Control Register

543620-29

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