LH543620 데이터 시트보기 (PDF) - Sharp Electronics

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LH543620

1024 × 36 Synchronous FIFO

Sharp Electronics 

1024 × 36 Synchronous FIFO

LH543620

Parity Checking

The Parity checking mechanism is always active. Par-

ity checking is done separately for each of the 9-bit bytes

of the 36-bit word read from the memory array. Toggling

Bit 0 of the control register selects odd or even parity.

When a parity error is detected in one or more bytes, the

signal PF is asserted and the result of the individual parity

checks are written to the parity register. See Example 3.

To avoid a possible invalid PF signal, ENO1 and ENO2

should not be deasserted during the CLKO low time.

The parity register is frozen until read. When read, the

parity register is released and ready to store the next

parity error data.

Parity Generation

After Reset, parity generation is not active. Parity

generation is active only when Bit 1 of the control register

is HIGH. The parity mechanism, when enabled, creates

a parity bit for each of the bytes of the input word. The

parity bit for each byte is created based on its 8 least

significant bits of each 9-bit byte of the input-data word

and on Bit 0 of the control register (it specifies odd or even

parity). The result of the parity generation is written back

to the MSB of the data byte. See Example 4.

PROGRAMMABLE RESOURCE REGISTERS

The LH543620 has six programmable resource regis-

ters. The resource registers may be loaded from either

the Input Port or the Output Port. They can be read from

the Output Port. The selection and loading or reading of

the resource registers is controlled by ADI, ADO and

CAPR. See Tables 1 and 4 and Figure 4.

The resource registers are:

Control (Default = 1).

AE Offset – Offset value of the AE flag (Default = 8).

AF Offset – Offset value of the AF flag (Default = 8).

RT Offset – Offset value of the Retransmit mechanism

(Default = 0).

RT Base – Base register of the Retransmit mechanism

(Default = 0).

Parity

EXAMPLE 3

Output word:

Odd parity:

Even parity:

PARITY CHECK

Q35

Q0

100111100 000111100 100111000 000111000

Parity Register = 0110; PF-Asserted Low

Parity Register = 1001; PF-Asserted Low

EXAMPLE 4

PARITY GENERATION

D35

D0

Input word:

100111100 000111100 100111000 000111000

Output, odd parity: 100111100 100111100 000111000 000111000

Output, even parity: 000111100 000111100 100111000 100111000

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