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FAN501MPX

Offline DCM / CCM Flyback PWM Controller for Charger Applications

Fairchild Semiconductor 

VDD Over-Voltage-Protection

VDD over-voltage protection prevents damage from over-

voltage exceeding the IC voltage rating. When VDD

exceeds 28 V due to an abnormal condition, protection

is triggered. This protection is typically caused by an

open circuit in the secondary-side feedback network.

Brownout Protection

Brownout protection is implemented through line voltage

detection circuit using the auxiliary winding, as shown in

Figure 26 and Figure 27. When the current flowing out

of the VS pin during the MOSFET conduction time is

smaller than 160 μA for longer than 30 ms, the brownout

protection is triggered.

Over-Temperature Protection (OTP)

If the junction temperature exceeds 140°C (TOTP), the

internal temperature-sensing circuit shuts down PWM

output and enters Latch Mode protection.

VS Under-Voltage Protection (VS UVP)

Generally, the fold-back point in CC regulation as output

drops is determined by the VDD-OFF level. Thus, the fold-

back level mainly depends on the characteristics of the

VDD diode and transformer. VS under-voltage protection

provides accurate fold-back point control to minimize the

effect from the external component tolerance. Figure 35

shows the internal circuit for VS UVP. By sampling the

auxiliary winding voltage on the VS pin around the end

of diode conduction time, the output voltage is indirectly

sensed. When VS sampling voltage is less than VVS-UVP

(1.55 V) longer than debounce cycles NVS-UVP, VS UVP

is triggered and the FAN501 enters Auto-Restart Mode.

To avoid VS UVP triggering during the startup sequence,

a startup blanking time, tVS-UVP-BLANK, (45 ms) in included

for system power on. For VS pin voltage divider design,

RVS1 is obtained from Equation (11) and RVS2 is

determined by VS UVP protection function as:

RVS 2



RVS1

 ( VO-UVP

VVS -UVP



NA

NS

- 1)-1

(11)

where VO-UVP is the output under-voltage protection level.

Aux.

RVS1

NA

RVS2

1.55V

3

S/H

DQ

Auto Restart

PWM

VSUVP

Dedounce time

Counter

VS Over-Voltage-Protect (VS OVP)

VS over-voltage protection prevents damage caused by

output over-voltage condition. Figure 36 shows the

internal circuit of VS OVP. When abnormal system

conditions occur that cause VS sampling voltage to

exceed VVS-OVP (3.2 V) for more than debounce

switching cycles (NVS-OVP), PWM pulses are disabled

and the FAN501 enters Latch Mode protection. VS over-

voltage conditions are usually caused by an open circuit

in the secondary-side feedback network or a fault

condition in the VS pin voltage divider resistors.

Aux.

RVS1

NA

RVS2

3.20V

S/H

DQ

Latch

Protection

PWM

VSOVP Dedounce

time

Counter

Figure 36. VS OVP Protection Circuit

Externally Triggered Shutdown

By pulling the SD pin voltage below threshold voltage,

VSD-TH (1.0 V); shutdown can be externally triggered and

the FAN501 enters Latch Mode protection. It can be

also used for external OTP protection by connecting an

NTC thermistor between the shutdown (SD)

programming pin and ground. An internal constant

current source, ISD (100 µA), introduces voltage drop

across the thermistor. Resistance of the NTC thermistor

becomes smaller as the ambient temperature increases,

which reduces the voltage drops across the thermistor.

When the voltage of the SD pin is less than threshold

voltage VSD-TH (1.0 V), OTP protection is triggered.

5V

NTC

Thermistor

100μA

1.0V

Latch

Protection

Figure 37. Thermal Shutdown Using SD Pin

Figure 35. VS UVP Protection Circuit

© 2014 Fairchild Semiconductor Corporation

FAN501 • Rev. 1.0.0

15

www.fairchildsemi.com

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