A6850KLTR-T(2011) 데이터 시트보기 (PDF) - Allegro MicroSystems
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A6850KLTR-T Datasheet PDF : 12 Pages
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A6850
Dual Channel Switch Interface IC
Signal and Enable delays
When ENABLEx = 1, current signals applied to the OUTPUTx
pins will appear scaled and delayed on the SENSEx pins. The
transfer characteristic can be considered that of a low pass filter.
The response time definitions are given in figures 1 and 2, in the
Characteristic Performance section.
The rise time response is dependent on the effective capacitance
loading on the SENSEx pin.
The RC time constant, , can be estimated using:
= RSENSEx (90 + CSENSE)
(2)
where RSENSEx is in kΩ and CSENSE is in pF; the result will
be in ns.
The 10% to 90% rise time, trLH , may be estimated from:
trLH= 2.2 ×
(3)
The small signal low pass filter bandwidth based on a single pole
response may be estimated using:
BW= 350 / trLH
(4)
The result is in MHz when trLH is in ns.
If the values of trLH and tfHL are significantly different then a bet-
ter estimate may be given by:
BW= 700 / (trLH + tfHL )
(5)
The result is in MHz when trLH and tfHL are in ns.
Each signal channel may be enabled or disabled individually via
their respective ENABLEx pins, as shown in table 1.
When a capacitor is added in parallel with the signal source con-
nected to an OUTPUTx pin, additional allowance must be made
for settling time caused by the inrush current needed to recharge a
partially, or fully discharged, capacitor which has decayed during
the disabled period.
During this time the current required may reach IOUTPUTM, the
current limit value for the OUTPUTx pins.
The effects will be most noticeable on a SENSEx pin and will
usually cause a signal overshoot as shown as tENsettle in figure 4.
Thermal Shutdown (TSD)
The A6850 protects itself from excessive heat damage by
disabling both outputs when the junction temperature, TJ , rises
above the TSD threshold (TTSD). The outputs will remain off
until the junction temperature falls below the TTSD level minus
the TSD hysteresis, TTSDhys.
ENABLEx
0 mA
OUTPUTx
50%
Table 1. Enable/Disable Signal Channel Truth Table
EN1
EN2
IOU1 IOU2 SEN1 SEN2
L*
L*
0
0
0
0
H
L
I1
0
I1 / 10
0
L
H
0
I2
0
I2 / 10
H
H
I1
I2
I1 / 10
I2 / 10
*Sleep mode
SENSEx
0V
tENdlyLH
tENsettle
Figure 4. Overshoot resulting from additional capacitance.
Allegro MicroSystems, Inc.
6
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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