A6850KLTR-T(2011) 데이터 시트보기 (PDF) - Allegro MicroSystems

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A6850KLTR-T
(Rev.:2011)

Dual Channel Switch Interface IC

Allegro MicroSystems 

A6850

Dual Channel Switch Interface IC

Functional Description

SENSE Pin Outputs

The A6850 divides the OUTPUTx pin current by 10 and mirrors

it onto the corresponding SENSEx pin. Putting sense resistors,

RSENSE , from these pins to ground will create a voltage that

can be read by an ADC (analog-to-digital converter). The value

of RSENSE should be chosen so that the voltage drop across the

sense resistor (VRSENSE) does not exceed the maximum voltage

rating of the ADC. For further protection of the ADC, an external

clamping circuit, such as a Zener diode, can be used to clamp any

transient current spikes that may occur on the output that would

be translated onto the SENSE pins.

Overvoltage Protection

The A6850 has built-in overvoltage protection against a load

dump on the supply bus. In the case of a load dump, or when VIN

is connected to the battery supply bus and VIN rises above the

overvoltage threshold, VOVP , the A6850 will shut off the outputs.

Sleep Mode

Low-leakage or sleep modes are required in automotive applica-

tions to minimize battery drain when the vehicle is parked. The

A6850 enters sleep mode when both ENABLE pins are low. In

sleep mode, the internal regulators and all other internal circuitry

are disabled.

The sense current is one tenth of the output current, plus an offset

current. This offset current is consistent across the whole range

of the output current. The sense current can be calculated by the

following formula:

When enabling an output, the part must first come out of sleep

mode. Consequently, the wake-up time amounts to a propagation

delay before the outputs turn on. Also, the ENABLE pins do not

switch with hysteresis until the regulators stabilize.

ISENSEx = (IOUTPUTx / 10) + ISENSE(ofs) .

(1)

The sense resistor must also be chosen to meet the voltage limits

on the sense pin (see Electrical Characteristics table).

After the internal regulators stabilize, internal circuitry is enabled

and the outputs turn on, as shown in figure 3. As long as one

ENABLE pin is held high, the A6850 operates with hysteresis.

Output Current Limit

The A6850 limits the output current to a maximum current of

IOUTPUTM. The output current will remain at the current limit

until the output load is reduced or the A6850 goes into thermal

shutdown.

The high output current limit allows the bypass capacitor, CBYP ,

on the Hall sensor IC to charge up quickly. This allows a high slew

rate on the VCC pin of the Hall sensor IC, ensuring that the sensor

IC Power-On State will be correct. See the Applications Informa-

tion section for schematic diagrams and power calculations.

Output Faults

The A6850 withstands short-to-ground or short-to-battery of the

OUTPUTx pins. In the case of short-to-ground, current is held to

the current limit (IOUTPUTM).

If VOUTPUTx > (VIN + 0.7 V) during a short-to-battery event, the

A6850 monitors VOUTPUTx and disables the outputs. Because the

protection circuitry requires a finite amount of time to disable the

outputs, a bypass capacitor of 1 μF is necessary on VIN. Although

OUTPUTx sinks current into the A6850 in this state, the reverse

current is shunted to ground and does not appear on the VIN pin.

ENABLE

VREG

VENABLEL

> tON

RegOk

OUTPUT

Figure 3. Activation Timing Diagram. Exiting Sleep mode via ENABLE

signal to output waveform.

Allegro MicroSystems, Inc.

5

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

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