LA7578N 데이터 시트보기 (PDF) - SANYO -> Panasonic

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LA7578N

IF Signal Processing (Super PLL-II VIF + SIF) Circuit for TVs and VCRs

SANYO -> Panasonic 

Fig. 26

LA7578N

Designing the external bleeder resistance ratio so that

the output DC voltage (V21) does not change when

the voltage is amplified by the equalizer amplifier

Assuming the desired gain is Av, then to make Vx 6 V21 so

that the sync signal voltage does not change:

Vx = VCC × R2/(R2 + R3) ................. : (1)

From the desired voltage gain:

Av = 1 + 1 k/Z1 .................................. : (2)

Z1 = R2 × R3/(R2 + R3) .................... : (3)

And then:

R2 = 1 k × VCC/[(VCC − Vx) × (Av−1)] ............: (4)

R3 = 1 k × VCC/[(Av − 1) × Vx] ........................: (5)

These simple calculations can be used to design the ratio.

Pin 22 (GND)

Connected to GND within the IC.

Pin 23 (GND)

Connected to GND within the IC.

Pin 24 (SIF input)

This is the SIF input pin.

The input impedance is approximately 1 kΩ. If an interfering

wave (video signal, etc.) flows into this input, it will generate a

buzz or buzz beat; therefore, caution must be exercised in

regard to the pattern layout for the input circuit. Fig. (B) below

shows a bad example.

Fig. 27

Ceramic BPF

pin 24

(A) Good example

Ceramic BPF

Pin 24

BPF input and output are close

to each other.

(B) Bad example

Fig. 28

No.4037-16/18

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