EF9345 데이터 시트보기 (PDF) - STMicroelectronics
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EF9345 Datasheet PDF : 38 Pages
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EF9345
MEMORY INTERFACE
VCC = 5.0V ±5%, TA = 0 to + 70°C
Clock : fin = 12MHz ; Duty Cycle 40 to 60% ; tr, tf < 5ns
Reference Levels : VIL = 0.8V and VIH = 2V, VOL = 0.4V and VOH = 2.4V
Symbol
tELEL
tD
tEHEL
tELDV
tDA
tAVEL
tELAX
tCLAZ
tGHDX
tOZ
tGLDV
tQVWL
tWHQX
tWLWH
Ident. N°
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Parameter
Memory Cycle Time
Output Delay Time from CLK Rising Edge (ASM, OE, WE)
ASM High Pule Width
Memory Access Time from ASM Low
Output Delay Time from CLK Rising Edge (ADM(0:7), AM(8:13))
Address Setup Time to ASM
Address Hold Time from ASM
Address Off Time
Memory Hold Time
Data Off Time from OE
Memory OE Access Time
Data Setup Time (Write Cycle)
Data Hold Time (Write Cycle)
WE Pulse Width
Min. Typ. Max. Unit
500
ns
60 ns
120
ns
290 ns
80 ns
30
ns
55
ns
80 ns
10
ns
60 ns
150 ns
30
ns
30
ns
110
ns
Figure 1 : Test Load
VDD
Test
Point
CL
RL
MMD7000
R
or equivalent
Table 1
Symbol
C
RL
R
AM(8:13)
ADM(0:7)
AD(0:7)
100pF
1kΩ
4.7kΩ
Other
Outputs
50pF
3.3kΩ
4.7kΩ
Figure 2 : Memory Interface Timing Diagram
T
1
CLK
2
ASM
4
2
56
8
7
3
5
56
7
ADM (0:7)
READ ADDRESS
D IN
WRITE ADDRESS
AM (8:14)
OE
WE
2
2
9
11
10
12
D OUT
2
2
14
13
5/38
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