IDT7027L55GG(2018) 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT7027L55GG Datasheet PDF : 20 Pages
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IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
AC Test Conditions
dInput Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns Max.
1.5V
1.5V
Figures 1 and 2
3199 tbl 11
DATAOUT
BUSY
INT
347Ω
Industrial and Commercial Temperature Ranges
5V
893Ω
DATAOUT
30pF
347Ω
5V
893Ω
5pF*
Figure 1. AC Output Test Load
3199 drw 04
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
*Including scope and jig.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Ranges(4)
7027X15
Com'l Only
7027X20
Com'l
& Ind
7027X25
Com'l
& Ind
7027X35
Com'l Only
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max.
READ CYCLE
tRC
Read Cycle Time
15
____
20
____
25
____
35
____
tAA
Address Access Time
____
15
____
20
____
25
____
35
tACE
Chip Enable Access Time(4)
____
15
____
20
____
25
____
35
tAOE
Output Enable Access Time
____
10
____
12
____
13
____
20
tOH
Output Hold from Address Change
3
____
3
____
3
____
3
____
tLZ
Output Low-Z Time(1,2)
3
____
3
____
3
____
3
____
tHZ
Output High-Z Time(1,2)
____
10
____
12
____
15
____
15
tPU
Chip Enable to Power Up Time(2,5)
0
____
0
____
0
____
0
____
tPD
Chip Disable to Power Down Time(2,5)
____
15
____
20
____
25
____
35
tSOP
Semaphore Flag Update Pulse (OE or SEM)
10
____
10
____
12
____
15
____
tSAA
Semaphore Address Access Time
____
15
____
20
____
25
____
35
NOTES:.
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE= VIH and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
5. Refer to Chip Enable Truth Table.
7027X55
Com'l Only
Min. Max. Unit
55
____
ns
____
55 ns
____
55 ns
____
30 ns
3
____
ns
3
____
ns
____
25 ns
0
____
ns
____
50 ns
15
____
ns
____
55 ns
3199 tbl 12
6.742
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