IDT7027L55GG(2018) 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT7027L55GG Datasheet PDF : 20 Pages
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IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,6) (VCC = 5.0V ± 10%)
7027X15
Com'l Only
7027X20
Com'l
& Ind
7027X25
Com'l
& Ind
Symbol
Parameter
Test Condition
Version
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max. Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
CE = VIL, Outputs Disabled
SEM = VIH
f = fMAX(3)
COM'L S 205
365
190
325
180
305
mA
L 200
325
180
285
170
265
IND
S
___
L
___
___
___
___
170
345
___
180
335
___
___
ISB1
Standby Current
(Both Ports - TTL Level
Inputs)
CEL = CER = VIH
SEMR = SEML = VIH
f = fMAX(3)
COM'L S 65
110
50
90
40
85
mA
L 65
90
50
70
40
60
IND
S
___
___
___
___
40
100
L
___
___
50
85
___
___
ISB2
Standby Current
(One Port - TTL Level
Inputs)
CE"A" = VIL and CE"B" = VIH(5)
COM'L S 130
245
115
215
105
200
mA
Active Port Outputs Disabled,
L 130
215
115
185
105
170
f=fMAX(3)
SEMR = SEML = VIH
IND
S
___
___
___
___
105
230
L
___
___
115
220
___
___
ISB3
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Both Ports CEL and
CER > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
SEMR = SEML > VCC - 0.2V
COM'L S 1.0
15
1.0
15
1.0
15
mA
L 0.2
5
0.2
5
0.2
5
IND
S
___
L
___
___
___
___
1.0
30
___
0.2
10
___
___
ISB4
Full Standby Current
(One Port - All CMOS
Level Inputs)
CE"A" < 0.2V and
COM'L S 120
220
110
190
100
170
mA
CE"B" > VCC - 0.2V(5)
L 120
190
110
160
100
145
SEMR = SEML > VCC - 0.2V
VIN > VCC - 0.2V or VIN < 0.2V
IND
S
___
___
___
___
100
200
Active Port Outputs Disabled
L
___
___
110
195
___
___
f = fMAX(3)
3199 tbl 10a
7027X35
Com'l Only
7027X55
Com'l Only
Symbol
Parameter
Test Condition
Version
Typ.(2)
Max.
Typ.(2)
Max.
Unit
ICC
Dynamic Operating Current
(Both Ports Active)
CE = VIL, Outputs Disabled
SEM = VIH
f = fMAX(3)
COM'L
S
160
295
150
270
mA
L 160
255
150
230
IND
S
___
___
___
___
L
___
___
___
___
ISB1
Standby Current
(Both Ports - TTL Level
Inputs)
CEL = CER = VIH
SEMR = SEML = VIH
COM'L
S
30
85
20
85
mA
L
30
60
20
60
IND
S
___
___
___
___
L
___
___
___
___
ISB2
Standby Current
(One Port - TTL Level
Inputs)
CE"A" = VIL and CE"B" = VIH(5)
Active Port Outputs Disabled,
f=fMAX(3)
SEMR = SEML = VIH
COM'L
S
95
185
85
165
mA
L
95
155
85
135
IND
S
___
___
___
___
L
___
___
___
___
ISB3
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Both Ports CEL and
CER > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
SEMR = SEML > VCC - 0.2V
COM'L
S
1.0
15
1.0
15
mA
L
0.2
5
0.2
5
IND
S
___
___
___
___
L
___
___
___
___
ISB4
Full Standby Current
(One Port - All CMOS
Level Inputs)
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
SEMR = SEML > VCC - 0.2V
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled
f = fMAX(3)
COM'L
S
90
160
80
135
mA
L
90
135
80
110
IND
S
___
___
___
___
L
___
___
___
___
NOTES:
3199 tbl 10b
1. 'X' in part numbers indicates power rating (S or L).
2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions” of input
levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Refer to Chip Enable Truth Table.
6.642
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