IDT7024S15PF 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT7024S15PF

HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7024S/L

HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM

AC TEST CONDITIONS

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V

5ns Max.

1.5V

1.5V

Figures 1 and 2

2740 tbl 12

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATAOUT

BUSY

INT

775Ω

5V

1250Ω

30pF

DATAOUT

775Ω

5V

1250Ω

5pF

Figure 1. AC Output Test Load

2740 drw 06

Figure 2. Output Test Load

(for tLZ, tHZ, tWZ, tOW)

Including scope and Jig

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)

Symbol

Parameter

IDT7024X15

Com'l. Only

Min. Max.

IDT7024X17

Com'l. Only

Min. Max.

IDT7024X20

Min. Max.

IDT7024X25

Min. Max. Unit

READ CYCLE

tRC

Read Cycle Time

15 —

17

—

20

—

25

— ns

tAA

Address Access Time

tACE

Chip Enable Access Time(3)

tABE

Byte Enable Access Time(3)

— 15

—

17

—

20

—

25 ns

— 15

—

17

—

20

—

25 ns

— 15

—

17

—

20

—

25 ns

tAOE

Output Enable Access Time

— 10

—

10

—

12

—

13 ns

tOH

Output Hold from Address Change

3

—

3

—

3

—

3

— ns

tLZ

Output Low-Z Time(1, 2)

3

—

3

—

3

—

3

— ns

tHZ

Output High-Z Time(1, 2)

—

10

—

10

—

12

—

15 ns

tPU

Chip Enable to Power Up Time(1,2)

0

—

0

—

0

—

0

— ns

tPD

Chip Disable to Power Down Time(1,2)

— 15

—

17

—

20

—

25 ns

tSOP

tSAA

Semaphore Flag Update Pulse (OE or SEM) 10 —

10

—

10

—

10

— ns

Semaphore Address Access(3)

— 15

—

17

—

20

—

25 ns

Symbol

Parameter

IDT7024X35

Min. Max.

IDT7024X55

Min. Max.

IDT7024X70

Mil. Only

Min. Max. Unit

READ CYCLE

tRC

Read Cycle Time

35

—

55

—

70

— ns

tAA

Address Access Time

tACE

Chip Enable Access Time(3)

tABE

Byte Enable Access Time(3)

—

35

—

55

—

70 ns

—

35

—

55

—

70 ns

—

35

—

55

—

70 ns

tAOE

Output Enable Access Time

—

20

—

30

—

35 ns

tOH

Output Hold from Address Change

tLZ

Output Low-Z Time(1, 2)

tHZ

Output High-Z Time(1, 2)

tPU

Chip Enable to Power Up Time(1,2)

tPD

Chip Disable to Power Down Time(1,2)

3

—

3

—

3

— ns

3

—

3

—

3

— ns

—

15

—

25

—

30 ns

0

—

0

—

0

— ns

—

35

—

50

—

50 ns

tSOP

Semaphore Flag Update Pulse (OE or SEM)

15

—

15

—

15

tSAA

Semaphore Address Access(3)

—

35

—

55

—

NOTES:

1. Transition is measured ±500mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = VIL, UB or LB = VIL, and SEM =VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM =VIL.

4. "X" in part numbers indicates power rating (S or L).

— ns

70 ns

2740 tbl 13

6.15

7

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