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IDT7024S15PF

HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7024S/L

HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING(1,5,8)

ADDRESS

OE

CE or SEM (9)

tWC

tAW

tHZ (7)

(9)

UB or LB

R/W

DATAOUT

DATAIN

tAS(6)

(4)

tWP(2)

tWZ (7)

tDW

tWR(3)

tOW

tDH

(4)

2740 drw 09

TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE, UB, LB CONTROLLED TIMING(1,5)

ADDRESS

CE or SEM(9)

UB or LB (9)

tAS(6)

tWC

tAW

tEW (2)

tWR(3)

R/W

tDW

tDH

DATAIN

2740 drw 10

NOTES:

1. R/W or CE or UB & LB must be High during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a Low UB or LB and a Low CE and a Low R/W for memory array writing cycle.

3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going High to the end-of-write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE, R/W, UB, or LB.

7. This parameter is guaranted by device characterization, but is not production tested. Transition is measured +/- 500mV steady state with the Output Test

Load (Figure 2).

8. If OE is Low during R/W controlled write cycle, the write pulse width must be the larger of tWP for (tWZ + tDW) to allow the I/O drivers to turn off and data

to be placed on the bus for the required tDW. If OE is High during an R/W controlled write cycle, this requirement does not apply and the write pulse

can be as short as the specified tWP .

9. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access Semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. tEW must be

met for either condition.

6.15

10

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