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BT8110

High-Capacity ADPCM Processor

Conexant Systems 

Bt8110/8110B

High-Capacity ADPCM Processor

2.0 Functional Description

2.2 Modes of Operation

2.2 Modes of Operation

This section details the functional timing of the clock, synchronization, and signal

interfaces. The data and control interfaces include the clock and synchronization

inputs, the PCM and ADPCM inputs and outputs, and the control inputs to select

algorithm reset, transparent operation, PCM code type, and the selected coding

algorithm when the microprocessor interface is not selected. The 24- or

32-channel full-duplex interleaved encoder and decoder operation is presented

first, followed by 48- or 64-channel encoder-only operation, and 48- or

64-channel decoder-only operation.

2.2.1 24- or 32-Channel Full-Duplex Interleaved Operation

Figure 2-3 illustrates the operation of the Bt8110/8110B in 24- or 32-channel

full-duplex interleaved mode with microprocessor control. The channel numbers

in parentheses are for the 24-channel full-duplex mode. In this diagram, inputs

are shown changing on negative edges of the input clock, and outputs are shown

changing on positive edges. This is the recommended method for operating the

Bt8110/8110B to avoid any timing problems. Detailed timing parameters are

given in Chapter 4.0.

To operate the Bt8110/8110B in the 24- or 32-channel full-duplex interleaved

mode, the Mode Control Register located at address 0x40 should be set to a value

of 0x0C for 32 channels, 0x04 for 24 channels.

In many 24-channel configurations, a gapped clock will be used to account for

the frame bit of the T1 signal; this operates correctly as long as there are exactly

32 clock cycles per channel processed.

100060C

Conexant

2-5

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