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BT8110

High-Capacity ADPCM Processor

Conexant Systems 

2.0 Functional Description

2.1 Overview

Bt8110/8110B

High-Capacity ADPCM Processor

Table 2-1. Signal Connections

Bt8110/8110B

Pin

Function

MICREN

µP Enable

ALE

WR*

CS

AD[0]

AD[1]

AD[2]

AD[3]

AD[4]

AD[5]

AD[6]

Address Latch Enable

Write Enable

Chip Select

Address/Data

Address/Data

Address/Data

Address/Data

Address/Data

Address/Data

Address/Data

Intel 8051

VCC

ALE

WR*

A[n]

AD[0]

AD[1]

AD[2]

AD[3]

AD[4]

AD[5]

AD[6]

Motorola 68HC11

VCC

AS

E

A[n]

AD[0]

AD[1]

AD[2]

AD[3]

AD[4]

AD[5]

AD[6]

The interface for the Intel 8051 or Motorola 68HC11 microprocessors

comprises the latch enable signal, the write enable (8051) or enable signal

(68HC11), the chip select signal (one pin from port P2 of the 8051) and the seven

low bits of the 8-bit address/data bus (port P0 of the 8051). For the 68HC11

microprocessor, the enable signal E is connected to the write enable pin. The

setup and hold times required for the latch enable and write enable signals are

10 ns. Other (much faster) processors can be used as long as the multiplexed

address/data bus feature of the 8051 is supported.

Detailed timing requirements for the microprocessor interface are given in

Section 4.1.

2.1.3 Address Map

The address map for the controller is given in the Register Summary, Table 3-3

and Table 3-4, where both interleaved and encoder/decoder operations are shown.

The internal control registers for the 32 encoders and the 32 decoders for

interleaved operation are located at addresses 0x00–0x3F. A write to address 0x40

will load the Mode Control Register [mode; 0x40].

2-4

Conexant

100060C

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