MX589 데이터 시트보기 (PDF) - MX-COM Inc

부품명

상세내역

일치하는 목록

MX589

High Speed GMSK Modem

MX-COM Inc  

High Speed GMSK Modem 4k to 64kbps

8

MX589

The output of the radio receiver's Frequency Discriminator should be fed to the MX589's RX Filter by a suitable gain and

DC level adjusting circuit. This circuit can be built with external components around the on-chip RX Input Amplifier. The

gain should be set so that the signal level at the RX Feedback pin is nominally 1V peak to peak (for VDD=5.0V) centered

around VBIAS when receiving a continuous 1111000011110000.. data pattern.

Positive going signal excursions at RX Feedback pin will produce a logic 0 at the RX Data Output. Negative going

excursions will produce a logic 1.

The received signal is fed through the lowpass RX Filter, which has a -3dB corner frequency of 0.56 times the data

bit-rate, before being applied to the Level Measure and Clock and Data extraction blocks.

The Level Measuring block consists of two voltage detectors, one of which measures the amplitude of the positive parts of

the received signal. The other measures the amplitude of the negative portions. (Positive refers to signal levels higher

than VDD/2, and negative to levels lower than VDD/2.) External capacitors are used by these detectors, via the Doc1 &

Doc2 pins, to form voltage ‘hold’ or ‘integrator’ circuits. These two levels are then used to establish the optimum DC level

decision-thresholds for the Clock and Data extraction, depending upon the RX signal amplitude and any DC offset.

4.2.2 Rx Circuit Control Modes

The operating characteristics of the Rx Level Measurement and Clock Extraction circuits are controlled, as shown in Table

5, by logic level inputs applied to the PLLacq, Rx HOLD , and RxDCacq pins to suit a particular application, or to cope with

changing reception conditions, reference Figure 5.

In general, a data transmission will begin with a preamble, for example, 1100110011001100, to allow the receive modem

to establish timing and level-lock as quickly as possible. After the Rx carrier has been detected, and during the time that

the preamble is expected, the RxDCacq and PLLacq Inputs should be switched from a logic 0 to a logic 1 so that the

Level Measuring and Clock Extraction modes are operated and sequenced as shown.

The Rx HOLD input should normally be held at a logic 1 while data is being received, but may be driven to a logic 0 to

freeze the Level Measuring Clock Extraction circuits during a fade. If a fade lasts for less than 200 bit periods, normal

operation can be resumed by returning the Rx HOLD input to a logic 1 at the end of the fade. For longer fades, it may be

better to reset the Level Measuring circuits by placing the RxDCacq to a logic 1 for 10 to 20 bit periods.

Rx HOLD has no effect on the Level Measuring circuits while RxDCacq is at a logic 1, and has no effect on the PLL while

PLLacq is at a logic 1.

A logic 0 on Rx HOLD does not disable the Rx Clock output, and the Rx Data Extraction and S/N Detector circuits will

continue to operate.

Rx Signal Input

PREAMBLE

DATA

Rx CARRIER DET

(RSSI) Input

RxDCacq

Rx LEVEL MEASURE

MODE

CLAMP

PLLacq

CLOCK EXTRACTION

CCT MODE

FAST PEAK

DETECT

ACQUIRE

AVERAGING PEAK

DETECT

30 BITS

MEDIUM

BANDWIDTH

NARROW

BANDWIDTH

Figure 5: Rx Mode Control Diagram

©1998 MX-COM, Inc.

www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054

Doc. # 20480103.010

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA

All trademarks and service marks are held by their respective companies.

Share Link: