NJG1707PG1 데이터 시트보기 (PDF) - Japan Radio Corporation
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NJG1707PG1 Datasheet PDF : 17 Pages
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NJG1707PG1
nTERMINAL INFORMATION
PIN NO. SYMBOL
DESCRIPTIONS
4
CTL1
5
CTL2
6
CTL3
7
VSS
9
VDD
11
EXT2
13
EXT1
15
TX
17
TER2
19
ANT1
21
RX
23
ANT2
25
TER1
26,27
28
30
GND(LNA)
LNAIN
LNAOUT
31
EXTCAP
1,2,3,8,10,
12,14,16,1
8,20,22,24,
29,32
GND
Control signal input terminal of high impedance C-MOS logic. Logic level: High; more
than +2V, Low; 0~+0.6V. Please connect to GND or VDD with 100kΩ if potential is
open or uncertain.
Negative supply terminal. Negative voltage of -3.5~-2.0V must be supplied on Tx
mode. This terminal is isolated on Rx mode, so open or –2.5~0V condition can be
used. Please connect bypass capacitor with GND to keep RF performance.
Positive supply terminal. The voltage of this terminal should be supplied before or
same time with other DC supplying terminals (CTL1~3, VSS). The bias voltage should
be +2.7~+5.0V. Please connect bypass capacitor with GND to keep RF performance.
RF port for Rx signal. A DC cut capacitor (56pF~100pF) is required to block VDD
voltage.
RF port for Tx/Rx signal. A DC cut capacitor (56pF~100pF) is required to block VDD
voltage.
Tx power input terminal. A DC cut capacitor is required to block VDD voltage, and also
an external matching circuit is required to improve VSWR(See Application circuit).
A termination terminal for ANT1 in case ANT2 is in use. The influence of ANT1
against ANT2 is reduced. A DC cut capacitor (10pF) is required to block VDD voltage.
RF port for Tx/Rx signal. A DC cut capacitor (56pF~100pF) is required to block VDD
voltage.
Rx output terminal. A DC cut capacitor is required to block VDD voltage, and also an
external matching circuit is required to improve VSWR(See Application circuit).
RF port for Rx signal. A DC cut capacitor (56pF~100pF) is required to block VDD
voltage.
A termination terminal for ANT2 in case ANT1 is in use. The influence of ANT2
against ANT1 is reduced. A DC cut capacitor (10pF) is required to block VDD voltage.
Ground terminal of LNA. Please place ground plane close to this pin for good RF
performance.
LNA input terminal. An external matching circuit is required.
LNA output terminal. An external matching circuit with LNA biasing element L3, L4 as
in application circuit is required.
Bypass capacitor terminal of LNA. Please place C9 as in application circuit close to
this terminal.
Ground terminal. Please connect to ground plane as close as possible for good RF
performance.
nTRUTH TABLE
”H”=VCTL (H), ”L”=VCTL (L), ”X”=H or L
CONTROL INPUT
CONTROL OUTPUT
ROUTE
Tx/Rx Diversity IN/OUT
SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 SW9
CTL1 CTL2 CTL3
Tx-ANT1
H
X
H OFF OFF OFF ON ON OFF OFF OFF ON
Tx-EXT1
H
X
L OFF OFF ON OFF ON ON ON OFF OFF
Rx-ANT1
L
L
H OFF OFF ON OFF ON OFF ON ON ON
Rx-ANT2
L
H
H
ON OFF OFF OFF OFF ON ON ON ON
Rx-EXT1
L
L
L OFF OFF OFF ON ON ON OFF ON OFF
Rx-EXT2
L
H
L OFF ON OFF OFF ON ON ON ON ON
-5-
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