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NCP1560

Full Featured Voltage Mode PWM Controller

ON Semiconductor 

NCP1560

If the soft−start period is too long, VAUX may discharge to

7.0 V before the converter output is completely in regulation

causing the outputs to be disabled. If the converter output is

not completely discharged when the outputs are reenabled,

the converter will eventually reach regulation exhibiting a

nonmonotonic startup behavior. But, if the converter output

is completely discharged when the outputs are reenabled, the

cycle may repeat and the converter will not start.

In the event of an UV, OV, or cycle skip fault, the soft−start

capacitor is discharged. Once the fault is removed, a

soft−start cycle commences. The soft−start steady state

voltage is approximately 4.1 V.

Control Outputs

The NCP1560 has two in−phase control outputs, OUT1

and OUT2, with adjustable overlap delay (tD). OUT2

precedes OUT1 during a low to high transition and OUT1

precedes OUT2 at any high to low transition. Figure 35

shows the relationship between OUT1 and OUT2.

tD (Leading)

OUT1

tD (Trailing)

OUT2

Figure 35. Control Outputs Timing Diagram

Generally, OUT1 controls the main switching element.

Output 2, once inverted, can control a synchronous rectifier.

The overlap delay prevents simultaneous conduction.

Output 2 can also be used to control an active clamp reset.

Once VAUX reaches 11 V, the internal startup circuit is

disabled and the One Shot Pulse Generator is enabled. If no

faults are present, the outputs turn ON. Otherwise, the

outputs remain OFF until the fault is removed and VAUX

reaches 11 V again.

The control outputs are biased from VAUX. The outputs

can supply up to 10 mA each and their high state voltage is

usually 0.2 V below VAUX. Therefore, the auxiliary supply

voltage should not exceed the maximum input voltage of the

driver stage.

If the control outputs need to drive a large capacitive load,

a driver should be used between the NCP1560 and the load.

ON Semiconductor’s MC33152 is a good selection for an

integrated driver. Figures 27 and 28 shows the relationship

between the output’s rise and fall times vs capacitive load.

Time Delay

The overlap delay between the outputs is set connecting

a resistor (RD) between the tD and VREF pins. An overlap

delay of 80 ns is obtained when RD is 60 kW. A higher delay

is obtained by increasing RD. As RD increases, the bias

current of the time delay circuit is reduced, increasing its

noise susceptibility. If a delay higher than 150 ns is required,

it is recommended to place a small capacitor between the tD

pin and ground.

The output duty cycle can be adjusted from 0% to 85%

selecting appropriate values of RFF and VDC(inv). It should

be noted that the overlap delay may cause OUT2 to reach

100% duty cycle. Therefore, if OUT2 is used, the maximum

duty cycle of OUT2 needs to be kept below 100%. The

maximum overlap delay, tD(max), depends on the maximum

duty cycle and frequency of operation. The maximum

overlap delay is calculated using the equation below.

tD(max)

v

(1

* DC)

2ƒ

For example, if the converter operates at a frequency of

300 kHz with a maximum duty cycle of 80%, the maximum

allowed overlap delay is 333 ns. However, this is a

theoretical limit and variations over the complete operating

range should be considered when selecting the overlap

delay.

Additional Information

A 100 W DC−DC converter for telecom systems is

designed and implemented using the NCP1560. The

converter delivers 100 W at 3.3 V and achieves a full load

efficiency of 85%. The system is built using a 4 layer FR4,

single sided board. The components location within the

board is shown in Figure 36 and the complete circuit

schematic is shown in Figure 37. The converter design is

discussed in Application Note AND8105/D. Please contact

your sales representative for board availability.

http://onsemi.com

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