M66255FP 데이터 시트보기 (PDF) - Renesas Electronics

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M66255FP

8192 × 10-Bit Line Memory (FIFO)

Renesas Electronics 

M66255FP

Variable Length Delay Bits

1-line (8192 Bits) Delay

A write input data is written into memory at the second rise edge of WCK in the cycle, and a read output data is output

from memory at the first rise edge of RCK in the cycle, so that 1-line delay can be made easily.

WCK

RCK

Cycle 0 Cycle 1 Cycle 2

tRESS tRESH

WRES

RRES

tDS tDH

Cycle 8192 Cycle 8193 Cycle 8194

Cycle 8190 Cycle 8191 (0')

(1')

(2')

tDS tDH

Dn

(0)

(1)

(2)

(8189)

(8190)

(8191)

(0')

(1')

(2')

(3')

8192 cycles

tAC

tOH

Qn

(0)

(1)

(2)

(3)

WE, RE = "L"

N-bit Delay Bit

(Making a reset at a cycle corresponding to delay length)

WCK

RCK

Cycle 0 Cycle 1 Cycle 2

tRESS tRESH

WRES

RRES

tDS tDH

Cycle n Cycle n + 1 Cycle n + 2 Cycle n + 3

Cycle n − 2 Cycle n − 1 (0')

(1')

(2')

(3')

tRESS tRESH

tDS tDH

Dn

(0)

(1)

(2)

(n − 3)

(n − 2)

(n − 1)

(0')

(1')

(2')

(3')

m cycles

tAC

tOH

Qn

(0)

(1)

(2)

(3)

WE, RE = "L"

m≥3

REJ03F0249-0200 Rev.2.00 Sep 14, 2007

Page 9 of 13

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