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CY62146EV30

4-Mbit (256 K × 16) Static RAM

Cypress Semiconductor 

Switching Characteristics

Over the Operating Range

Parameter [14, 15]

Description

Read Cycle

tRC

tAA

tOHA

tACE

tDOE

tLZOE

tHZOE

tLZCE

tHZCE

tPU

tPD

tDBE

tLZBE

tHZBE

Write Cycle [18]

tWC

tSCE

tAW

tHA

tSA

tPWE

tBW

tSD

tHD

tHZWE

tLZWE

Read cycle time

Address to data valid

Data hold from address change

CE LOW to data valid

OE LOW to data valid

OE LOW to Low-Z [16]

OE HIGH to High-Z [16, 17]

CE LOW to Low-Z [16]

CE HIGH to High-Z [16, 17]

CE LOW to power up

CE HIGH to power down

BLE / BHE LOW to data valid

BLE / BHE LOW to Low-Z [16]

BLE / BHE HIGH to High-Z [16, 17]

Write cycle time

CE LOW to write end

Address setup to write end

Address hold from write end

Address setup to write start

WE pulse width

BLE / BHE LOW to write end

Data setup to write end

Data hold from write end

WE LOW to High-Z [16, 17]

WE HIGH to Low-Z [16]

CY62146EV30 MoBL®

45 ns

(Industrial /

Automotive-A)

Unit

Min

Max

45

–

ns

–

45

ns

10

–

ns

–

45

ns

–

22

ns

5

–

ns

–

18

ns

10

–

ns

–

18

ns

0

–

ns

–

45

ns

–

22

ns

5

–

ns

–

18

ns

45

–

ns

35

–

ns

35

–

ns

0

–

ns

0

–

ns

35

–

ns

35

–

ns

25

–

ns

0

–

ns

–

18

ns

10

–

ns

Notes

14.

Test conditions for all parameters other

pulse levels of 0 to VCC(typ), and output

than tri-state parameters assume signal transition time

loading of the specified IOL/IOH as shown in the Figure

of 3 ns (1 V/ns)

3 on page 5.

or

less,

timing

reference

levels

of

VCC(typ)/2,

input

15. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.

16.

At any given

device.

temperature

and

voltage

condition,

tHZCE

is

less

than

tLZCE,

tHZBE

is

less

than

tLZBE,

tHZOE

is

less

than

tLZOE,

and

tHZWE

is

less

than

tLZWE

for

any

given

17. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.

18.

The internal write

these signals can

time of the memory

terminate a write by

is defined by the overlap of

going INACTIVE. The data

iWnpEu,tCsEetu=pVaILn,dBhHoEldatnimd/inogr

BmLuEst=bVeILre. fAelrlesnigcneadlstomthuestebdegeACofTtIhVeEstiogninailtitahtaet

a write and

terminates

any of

the write.

Document Number: 38-05567 Rev. *H

Page 7 of 18

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