AD7866(Rev0) 데이터 시트보기 (PDF) - Analog Devices
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AD7866 Datasheet PDF : 20 Pages
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AD7866
THE PART ENTERS
PARTIAL POWER-DOWN
THE PART BEGINS
TO POWER-UP
THE PART ENTERS
FULL POWER-DOWN
CS
SCLK
12
10
16
12
10
16
DOUTA
DOUTB
INVALID DATA
THREE-STATE
INVALID DATA
Figure 19. Entering Full Power-Down Mode
THREE-STATE
THE PART BEGINS
TO POWER UP
CS
1
SCLK
tPOWER UP
10
16
THE PART IS
FULLY POWERED UP
1
16
DOUTA
DOUTB
INVALID DATA
Figure 20. Exiting Full Power-Down Mode
VALID DATA
time is typically 4 µs; but if an external reference is being used, the
power-up time is typically 1 µs. This means that with any fre-
quency of SCLK up to 20 MHz, one dummy cycle will always be
sufficient to allow the device to power up from Partial Power-Down
(see Figure 18) when using an external reference. Once the dummy
cycle is complete, the ADC will be fully powered up and the input
signal will be acquired properly. A dummy cycle may well be suffi-
cient to power up the part when using an internal reference also,
provided the SCLK is slow enough to allow the required power-
up time to elapse before a valid conversion is requested. In addition
to this, it should be ensured that the quiet time, tQUIET, has still
been allowed from the point where the bus goes back into three-
state after the dummy conversion to the next falling edge of CS.
Alternatively, instead of slowing the SCLK to make the dummy
cycle long enough, the CS high time could just be extended to
include the required power-up time as in Figure 20 when power-
ing up from Full Power-Down.
The difference in the power-up time needed, when coming out
of Partial Power-Down, between the two cases where an internal
or external reference is being used, is primarily due to the on-chip
reference buffers. These power down in Partial Power-Down
mode and must be powered up again if the internal reference is
being used, but do not need to be powered up again if an exter-
nal reference is being used. The time needed to power these
buffers up is not just their own power-up time but also the time
required to charge up the decoupling capacitors present on the
pins VREF, DCAPA, and DCAPB.
It should also be noted that when powering up from Partial
Power-Down, the track-and-hold, which was in hold mode
while the part was powered down, returns to track mode after
the first SCLK edge the part receives after the falling edge of
CS. This is shown as point A in Figure 18.
When power supplies are first applied to the AD7866, the ADC
may power up in either of the power-down modes or the normal
mode. Because of this, it is best to allow a dummy cycle to elapse to
ensure the part is fully powered up before attempting a valid con-
version. Likewise, if it is intended to keep the part in the partial
power-down mode immediately after the supplies are applied,
two dummy cycles must be initiated. The first dummy cycle must
hold CS low until after the 10th SCLK falling edge (see Figure 16);
in the second cycle CS must be brought high before the 10th
SCLK edge but after the second SCLK falling edge (see Figure 17).
Alternatively, if it is intended to place the part in Full Power-
Down mode when the supplies have been applied, three dummy
cycles must be initiated. The first dummy cycle must hold CS low
until after the 10th SCLK falling edge (see Figure 16); the
second and third dummy cycles place the part in Full Power-
Down (see Figure 19). See the Modes of Operation section.
Once supplies are applied to the AD7866, enough time must be
allowed for any external reference to power up and charge any
reference capacitor to its final value, or enough time must be
allowed for the internal reference buffer to charge the various
reference buffer decoupling capacitors to their final values. Then,
to place the AD7866 in normal mode, a dummy cycle (1 µs to
4 µs approximately) should be initiated. If the first valid con-
version is then performed directly after the dummy conversion,
care must be taken to ensure that adequate acquisition time has
been allowed. As mentioned earlier, when powering up from the
power-down mode, the part will return to track upon the first
SCLK edge applied after the falling edge of CS. However, when
the ADC powers up initially after supplies are applied, the track-
and-hold will already be in track. This means that (assuming one
has the facility to monitor the ADC supply current) if the ADC
powers up in the desired mode of operation and thus a dummy
cycle is not required to change mode, then neither is a dummy
cycle required to place the track-and-hold into track. If no current
monitoring facility is available, the relevant dummy cycle(s)
should be performed to ensure the part is in the required mode.
–16–
REV. 0
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