AD6620S 데이터 시트보기 (PDF) - Analog Devices
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AD6620S Datasheet PDF : 44 Pages
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AD6620
TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 11
EXPLANATION OF TEST LEVELS . . . . . . . . . . . . . . . . 11
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 12
PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . 13
INPUT DATA PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
OUTPUT DATA PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
FREQUENCY TRANSLATOR . . . . . . . . . . . . . . . . . . . . . 19
SECOND ORDER CASCADED INTEGRATOR
COMB FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
FIFTH ORDER CASCADED INTEGRATOR
COMB FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
RAM COEFFICIENT FILTER . . . . . . . . . . . . . . . . . . . . . 25
CONTROL REGISTERS AND ON-CHIP RAM . . . . . . . 27
PROGRAMMING THE AD6620 . . . . . . . . . . . . . . . . . . . 30
ACCESS PROTOCOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
MICROPORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . 32
SERIAL PORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . 35
JTAG BOUNDARY SCAN . . . . . . . . . . . . . . . . . . . . . . . . 37
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
ARCHITECTURE
As shown in Figure 1, the AD6620 has four main signal pro-
cessing stages: a Frequency Translator, two Cascaded Integrator
Comb FIR Filters (CIC2, CIC5), and a RAM Coefficient FIR
Filter (RCF). Multiple modes are supported for clocking data
into and out of the chip. Programming and control is accom-
plished via serial and microprocessor interfaces.
Input data to the chip may be real or complex. If the input data
is real, it may be clocked in as a single channel or interleaved
with a second channel. The two-channel input mode, called
Diversity Channel Real, is typically used in diversity receiver
applications. Input data is clocked in 16-bit parallel words,
IN[15:0]. This word may be combined with exponent input bits
EXP[2:0] when the AD6620 is being driven by floating-point or
gain-ranging analog-to-digital converters such as the AD6600.
Frequency translation is accomplished with a 32-bit complex
Numerically Controlled Oscillator (NCO). Real data entering
this stage is separated into in-phase (I) and quadrature (Q)
components. This stage translates the input signal from a digital
intermediate frequency (IF) to baseband. Phase and amplitude
dither may be enabled on-chip to improve spurious performance
of the NCO. A phase offset word is available to create a known
phase relationship between multiple AD6620s.
Following frequency translation is a fixed coefficient, high speed
decimating filter that reduces the sample rate by a program-
mable ratio between 2 and 16. This is a second order, cascaded
integrator comb FIR filter shown as CIC2 in Figure 1. (Note:
Decimation of 1 in CIC2 requires 2× or greater clock into
AD6620). The data rate into this stage equals the input data
rate, fSAMP. The data rate out of CIC2, fSAMP2, is determined by
the decimation factor, MCIC2.
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 44
RCF
3
EXP[2:0]
IN[15:0] 16
INPUT
DATA
INTERLEAVE
CIC5
MULTI-
PLEXER
DE-
INTERLEAVE
I-RAM
256 ؋ 18
C-RAM
256 ؋ 20
Q-RAM
256 ؋ 18
MRCF
FREQUENCY 3
TRANSLATOR
I 18
16
Q 18
EXP
SCALING
CIC2
SCALING
MCICS
MULTI-
PLEXER
SCALING MCICS
fSAMP5
23
23
COMPLEX
NCO
PHASE
OFFSET
CLK
A/B
RESET
TIMING
SYNC NCO
fSAMP2
EXPLNV,
EXPOFF
fSAMP
RCF COEFFICIENTS
NUMBER OF TAPS
CIC2, CIC5
DECIMATE FACTORS
DECIMATE FACTOR
ADDRESS OFFSET
NCO FREQUENCY
PHASE OFFSET
DITHER
SCALE FACTORS
OUTPUT
SCALE
FACTOR
SYNC MASK
CONTROL REGISTERS
INPUT MODE
REAL, DUAL, COMPLEX
FIXED OR WITH EXPONENT
SYNC M/S
MICROPORT AND
SERIAL ACCESS
SYNC CIC
SYNC RCF
SYNC
I/O
JTAG
MICROPROCESSOR INTERFACE
OUTPUT
SCALING, SOUT
MULTIPLEXER
PARALLEL
16
SERIAL
DVOUT
I/QOUT
A/BOUT
PARALLEL
OUTPUTS 16
AND
SERIAL I/O
TRST TCK TMS TDI TDO D[7:0] A[2:0] CS R/W DS DTACK MODE PAR/SER
(W/R) (R/D) (RDY)
OUT[15:0]
SCLK
SDI
SDO
SDFS
SDFE
SBM
WL[1:0]
AD
SDIV[3:0]
Figure 1. Block Diagram
–2–
REV. A
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