AD6620S 데이터 시트보기 (PDF) - Analog Devices

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AD6620S

67 MSPS Digital Receive Signal Processor

Analog Devices 

AD6620

MICROPORT MODE1, READ

Timing is synchronous to CLK; MODE = 1.

t DD

t HC

CLK1

N

N+1

N+2

N+3

N+4

N

R/W2

t SC

DS2

CS3

t ZR

D[7:0]

t SAM

A[2:0]

DTACK

tSC tHC

t ZD

DATA VALID

ADDRESS VALID

t DTACK

t HA

t DTACK

NOTES:

1 DTACK IS DRIVEN LOW ON THE RISING EDGE OF CLK "N+3" FOR INTERNAL ACCESS (A[2:0] = 000),

CLK "N=2" OTHERWISE.

2 THE SIGNAL, R/W MAY REMAIN HIGH AND DS MAY REMAIN LOW TO CONTINUE READ MODE.

3 CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+4 SHOWN) TO COMPLETE ACCESS

AND FORCE DTACK HIGH.

Figure 19. MODE1 Read Timing Requirements and Switching Characteristics

MICROPORT MODE1, WRITE

Timing is synchronous to CLK; MODE = 1.

CLK1

t SC

N

t HC

N+1

N+2

N+3

N*

R/W2

DS2

CS3

D[7:0]

A[2:0]

t SAM

t SAM

DATA VALID

ADDRESS VALID

t SC

t HC

t HM

t HA

DTACK

t DTACK

t DTACK

NOTES:

1 ON RISING EDGE OF "N+3" CLK, DTACK IS DRIVEN LOW.

2 THESE SIGNALS (R/W AND DS) MAY REMAIN IN LOW STATE TO CONTINUE WRITING DATA.

3 CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+3 SHOWN) TO COMPLETE WRITE

AND FORCE DTACK HIGH.

* THE NEXT WRITE MAY BE INITIATED ON CLK, N*.

Figure 20. MODE1 Write Timing Requirements and Switching Characteristics

–10–

REV. A

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